Questions tagged [vlsi]
VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.
331
questions
6
votes
2
answers
750
views
How to decide sizes for transistors in a design? What does it mean to design an IC?
I have recently started designing analog ICs as part of my academic work. So far all I do is take topologies given in textbooks or papers and try to design them in the PDKs available at my university. ...
- 505
0
votes
0
answers
19
views
FD-SOI Channel formation with fully depleted body
In an FD-SOI the body is undoped, which could be just an intrinsic semiconductor such as silicon. What I'm wondering is how the channel is formed in an FD-SOI when the body isn't doped at all. My ...
- 33
1
vote
0
answers
67
views
Specific, practical examples of limits of logic gate fan-in?
I've been looking around for discrete, specific, and practical answers to the question "how many inputs can a (N)AND/(N)OR gate have?" as it relates to ASIC/VLSI/MOSFET/semiconductor ...
0
votes
0
answers
23
views
Clock feedthrough of the bootstrapped switch
I'm learning about the bootstrapped switch through this paper. Razavi used a 20 µm / 28 nm NMOS (M1) as the main switch to achieve low Ron. I am wondering does this wide device cause any problem ...
- 625
0
votes
1
answer
43
views
How does analog IC benefit from channel length shrinking?
I have some experience in OTA design for both 180 nm and 130 nm technologies. I didn't see much advantage of using 130 nm, as I had to use quite long channel length to achieve an acceptable gain in ...
- 625
0
votes
0
answers
44
views
How to implement 2 stage pre-decoding
I've been studying VLSI and I came across a design problem regarding decoders.
Let's same I want to design a 12:4096 decoder using inverters, NAND 3 and NOR4 gates. Implementing this decoder without ...
1
vote
2
answers
144
views
can someone explain the working /operation of FinFET?
Any resources that give in depth analysis of FinFET working would be helpful.
I read a couple of papers on IEEE but most of them had very little information related to the working principle.
user373485
0
votes
0
answers
38
views
Transistors sizing on commercial VLSI custom design projects
I have a doubt regarding the way circuits sizing is carried out in custom design style commercial projects.
For example, let consider the design of a fast adder for a high performance CPU.
At logical ...
1
vote
2
answers
113
views
Why simulation of single NMOS/PMOS on LTspice has big difference with manual calculation using Level 1 Standard Parameters?
I am researching the mode of operation on PMOS and NMOS using Level 1 standard parameters.
This is the information of the NMOS circuit to be designed.
Using transistor model level 1 parameters, ...
- 41
0
votes
0
answers
16
views
In vlsi physical design ,what are the concepts to check for high standard cell growth?
What are the different checks that are usually done when there is a high standard cell growth from one stage to the next.
Eg: from place to CTS of there is a high standard cell growth what could be ...
- 111
0
votes
1
answer
58
views
A question about layout: How to connect the gate to metal 1 layer?
I'm trying to draw a NMOS as shown above, but have some problems (the figure is from Razavi's book, the green box I added represents the N implant layer)
In the process I used, there's a design rule ...
- 625
15
votes
1
answer
2k
views
What is the standard procedure for analogue IC tapeout?
This is probably a very broad question and I will try to be more specific. I'm asking this question to get a sense of the gap between my knowledge and a 'successful' tapeout, as I've heard many people ...
- 625
-2
votes
2
answers
105
views
Why are interrupts active low? [closed]
Came across this question recently and saw some answers too, but need a simple answer which is easy to understand.
1
vote
1
answer
144
views
On DC transfer characteristics, logic levels, and the static discipline
One thing that's confused me ever since I started studying digital design is what it means when books say, roughly, that we can choose or define the input and output thresholds for a given circuit ...
- 1,161
0
votes
0
answers
48
views
Issue in understanding routing in VLSI CAD
I have chosen to undertake VLSI CAD as a part of my electronics degree and I came across this statement (Source : Naveed Sherwani, Algorithms for VLSI Physical Design Automation, 3rd edition , Chapter ...
- 9
0
votes
2
answers
157
views
How does the second flip-flop in a naive synchronizer "prevent a metastable state from propagating"?
In this very nice answer it's explained that, fundamentally, a two flip-flop synchronizer's basic operation is to prevent the propagation of a metastable state (effectively, an invalid logic level) ...
- 1,161
2
votes
1
answer
240
views
Understanding the rigorous definition of hold time
Consider the attached from Weste and Harris's (WH) CMOS VLSI Design. I follow all of the discussion and definitions except for the hold time definition.
Now I am familiar with the common/heuristic ...
- 1,161
0
votes
1
answer
121
views
Why do I need multiple segments to model the RC flight time of interconnect?
Consider a problem where we are interested in computing the delay for a signal to propagate to some load capacitance after a step input on the driving logic gate, and let there be a nonnegligible ...
- 1,161
0
votes
0
answers
22
views
Does minimizing stages necessarily give best outcome when designing circuit under a delay constraint?
In the context of digital design, a common situation is to have to design a circuit for minimum energy under a delay constraint. Suppose a given circuit can be implemented with various stages. Is it ...
- 1,161
0
votes
2
answers
104
views
Why do we need output isolation for power-gated blocks?
In their CMOS VLSI Design, Weste and Harris give the following discussion of power gating a block of logic:
I am in particular interested in understanding the need for output isolation here. Is the ...
- 1,161
1
vote
0
answers
76
views
Calculate Acitivity Factor in VLSI
Here is the problem:
And this is my solution: activity factor = probility output node is 1 x (1 - probility output node is 1)
Source: E., W.N.H. and Harris, D.M. (2011) CMOS VLSI Design: A circuits ...
- 401
1
vote
1
answer
256
views
On different well processes (fabrication process)
My textbook (Weste and Harris's CMOS VLSI Design) is trying to explain to me the nature of fabricating wells in the twin-well and triple-well processes. My question here is about how we can use so few ...
- 1,161
2
votes
2
answers
207
views
On different well processes (reasons)
My textbook (Weste and Harris's CMOS VLSI Design) is trying to explain to me the difference between n-well, twin-well, and triple-well processes. My question here is about the reasons why we want to &...
- 1,161
0
votes
0
answers
100
views
Why does input threshold occur at the unique voltage at which both inverter MOSFETs are in saturation?
A relevant figure of merit for a CMOS inverter is the so-called input threshold voltage (no relationship to the threshold voltage of a given MOSFET) \$V_{inv}\$, defined as the voltage \$V_{in}\$ at ...
- 1,161
1
vote
1
answer
141
views
Justification for equivalent gate capacitance simplification in digital circuits
A MOSFET is, in reality, a four-terminal device with capacitances between each pair of terminals:
These capacitances are, of course, the standard MOSFET intrinsic and extrinsic differential ...
- 1,161
0
votes
1
answer
53
views
What does optimizing fabs "for throughput rather than latency" mean?
In the context of a whirlwind tour of the modern VLSI design, tapeout, and fabrication flow in their CMOS VLSI Design, Weste and Harris write the following:
Multiple chips are manufactured ...
- 1,161
0
votes
2
answers
435
views
Why do we alternate directions between metal layers?
In their CMOS VLSI Design and in the context of a discussion about the initial stages of floorplanning/physical design, Weste and Harris write that
Another important decision during floorplanning is ...
- 1,161
0
votes
1
answer
151
views
Why do two nonoverlapping phase completely obviate the possibility of hold time issues?
In Weste and Harris's CMOS VLSI Design, they write
In Section 10.2.5 we will see that flip-flops may experience hold-time failures if the system has too much clock skew, i.e., if one flip-flop ...
- 1,161
0
votes
1
answer
69
views
When working with a technology node (say 14nm), should I keep the gate lengths of the FETs strictly equal to the minimum gate length?
When doing simulations with a technology node, say 14nm, can I change the gate lengths of FETs as per my wish?
If I need a FET with 140nm gate length, should I set the gate length of the transistor ...
- 179
1
vote
1
answer
87
views
What does ‘full custom’ really mean?
It’s common in my intro digital logic/VLSI textbooks to see mention of “full custom” chips versus ASIC chips. I’m interested in understanding the difference between the two in the context where both ...
- 1,161