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Figure from Razavi's book

I'm trying to draw a NMOS as shown above, but have some problems (the figure is from Razavi's book, the green box I added represents the N implant layer)

In the process I used, there's a design rule saying the N/P implant layer needs to enclose the poly layer by a certain distance. So the layout in the figure won't pass DRC because the poly layer exceeds the boundary of N implant. I then dragged the green box to completely enclose the poly fingers to pass the DRC. Will this cause any problems?

In addition, are there any other ways to connect the gate to metal layers? I tried to add a via directly on the gate, but the DRC refused to accept it.

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It depends on process details, but it's pretty common to not allow a metal to poly via on top of a transistor, no matter how wide the gate is.

The entire poly layer needs to get implanted, otherwise the gate doping is wrong (and possibly almost zero). Making the implant layer larger only implants field oxide, so it won't matter if you make it extra large.

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  • \$\begingroup\$ To add to this, some processes allow you to run a poly from an nFET gate to a pFET gate, even though it needs to cross between implant layers - if so, the design rules will indicate how to properly abut the two. Of course, crossing on metal is also an option (which you may as well do anyway if you need gate metal straps for performance) if you cannot meet the design rules for this abutment or it's forbidden by your process. \$\endgroup\$
    – nanofarad
    Commented May 2 at 18:23

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