I've been studying VLSI and I came across a design problem regarding decoders.
Let's same I want to design a 12:4096 decoder using inverters, NAND 3 and NOR4 gates. Implementing this decoder without pre-decoding would be using 4096*(4NAND3 + 1NOR4) gates, basically every combination of the inputs.
Using pre-decoding, we could use way fewer gates by making 4 groups of 8 NAND3 gates. The first group would take as inputs a0',a1',a2', a0,a1',a2', .... a0,a1,a2 for a total of 8 outputs. Do this 3 more times with the other 3 groups for a total of 32 NAND gates. Finally, we use 4096 NOR4 gates to combine all these outputs to get our final output.
This is all very clear to me. However, I don't understand how we can make a decoder with 2 stages of pre-decoding. I searched in books and the internet for an implementation of a 3 stage decoder (2 stage pre-decoding and one final stage) and didn't get anything. The problem clearly specifies that there need to be 2 stages of pre-decoding using NAND3 and NOR4 gates while my answer only includes one. Any info on this matter would be greatly apreciated.
