All Questions
12
questions
1
vote
1
answer
2k
views
How to automatically add signals in GTKwave when opened?
I use GHDL and GTKwave to compile/simulate and see the waveform of my VHDL code. Is there any way to automatically append signals in GTKwave's signals window when opened?
The problem is that I ...
- 13
0
votes
2
answers
2k
views
How can I generate a 1 Hz clock from 100 MHz clock using VHDL?
How can I generate a 1 Hz clock from 100 MHz clock using VHDL?
...
- 1
0
votes
2
answers
644
views
Errors in VHDL code
The VHDL code was written by me for a 4-bit PIPO DFF register. I have been encountering some errors when i did so. Kindly check the code and errors below.
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2
votes
2
answers
577
views
Demo of designing a modern CPU in Verilog/VHDL [closed]
Please help me understand how such huge and complex devices like modern CPUs' are designed - would it be possible to see an example of some final circuit with billions of transistors made with Verilog/...
- 123
2
votes
2
answers
2k
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Verilog code to drive a signal high always
I am learning Verilog fundamentals recently. I want to drive a signal always high using reg. I wrote this and it didn't work.
...
- 2,772
1
vote
2
answers
1k
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Edge aligned Source synchronous outputs
This is a basic block diagram of source synchronous interface I found in altera document.
Here
This is how edge aligned source synchronous output looks like.
They say the reciever will shift the ...
- 2,772
1
vote
2
answers
1k
views
Synthesising "constant" in VHDL
From point of view of a synthesiser, is there any difference between:
Signal offset: std_logic_vector ( 3 downto 0) := "0100";
Constant offset: std_logic_vector ( 3 downto 0) := "0100&...
- 2,772
3
votes
1
answer
704
views
Timing Constraints
I need to sample 24-bit data on a DAC at 25 MHz. The data comes from a design, I implemented on FPGA. In every clock cycle, the FPGA outputs a 24-bit data, which the DAC has to sample in the next ...
- 11k
7
votes
1
answer
15k
views
Get_ports vs Get_pins vs Get_nets vs Get_registers
I am doing a design in vhdl for FPGA. I have a top level design which consists of 3 components: clock divider, Module_1 and Module_2. Top level entity has a clock input port. This clock is divided by ...
- 11k
0
votes
1
answer
458
views
Any open source alternative to MyHDL?
Is there any open source alternative to MyHDL? I have started learning but finding it very difficult.
0
votes
1
answer
621
views
Nesting entities in VHDL (Altera Quartus)
I want to ask a question. I'm trying to simulate a cpu. I did my schema and basically there are two logical parts of the CPU.
The first part is composed of a FIFO buffer, Cache memory for ...
- 129
0
votes
1
answer
771
views
How to reduce an ALU logic with the minimum logic possible? Its very challenging
Our professor wants us to reduce 8-function ALU (8 outputs) to a 4 out ALU that has the capability to implement all the 8 functions. We can use any gates(even AOI's), muxes, and can create our control ...
- 201