All Questions
9
questions
0
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1
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121
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Why do I need multiple segments to model the RC flight time of interconnect?
Consider a problem where we are interested in computing the delay for a signal to propagate to some load capacitance after a step input on the driving logic gate, and let there be a nonnegligible ...
- 1,161
0
votes
0
answers
22
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Does minimizing stages necessarily give best outcome when designing circuit under a delay constraint?
In the context of digital design, a common situation is to have to design a circuit for minimum energy under a delay constraint. Suppose a given circuit can be implemented with various stages. Is it ...
- 1,161
4
votes
3
answers
3k
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Propagation and contamination delays with different delays for rising and falling edges
In the Digital Design and Computer Architecture by David Harris, Sarah Harris the authors explain what are propagation delay and contamination delay in the following way:
The propagation delay \$t_{...
- 143
0
votes
1
answer
2k
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Why Tcd and Tpd is different in combinational ckt?
In book Harris & Harris , there is a statement that Contamination delay \$T_{cd}\$, and Propagation delay \$T_{pd}\$ are different due to following reasons:
Different rising and falling delays,
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0
votes
1
answer
859
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Load capacitance in CMOS circuits
I am studying VLSI and I have a question. What happens if we don't use output load in CMOS circuits? What happens to overshoot/undershoot and circuit delay?
2
votes
4
answers
2k
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Why propagation delay is measured at 50% of the input and output waveform?
I didn't find the concept of propagation delay measured at a particular point on the waveform.
- 21
1
vote
1
answer
175
views
Logical effort and delay estimation
So as I have understood the logical effort for a 2 input nand gate with only one of the inputs active = 4/3. Furthermore the net logical effort is 8/3 (considering both the inputs). Now given that the ...
- 35
1
vote
1
answer
290
views
why is contamination delay lower bound?
I am taking a course from edX called computation structures: 1.Digital Circuits. When the course explained about CMOS timing, there was propagation delay(tpd) and contamination delay(tcd). I ...
- 49
0
votes
1
answer
254
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falling delay inverters VLSI CMOS
How do I obtain the falling delay driving by signal A:
Data:
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- 11