Questions tagged [vlsi]
VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.
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Reducing the offset voltage of a source follower
I am currently trying to reduce the offset voltage of the circuit attached below to less than +/- 2mV over a 1V to 4V input range.
I have a few constraints for this task:
I can use ...
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Why does the body effect result in these \$V_{OH}\$ and \$V_{OL}\$ values?
Consider the following circuit and discussion which come from my textbook (Brown and Varnesic Fundamentals of Digital Logic):
Of course, the exercise is to notice that NMOS and PMOS are very bad in a ...
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RHP pole of two stage OTA
I learnt that for any amplifier (with some capacitor) if we short/open the capacitor and the polarity of gain changes, it is a sign of RHP zero.
Now, while applying the same analysis I obsevred that ...
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Confusion about time borrowing
After studying timing analyzing in FPGA I still have some confusions about time borrowing like the following:
I have seen some of this site EE having good reputation saying that time borrowing is ...
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Uncertainty(jitter) in setup and hold calculation
In setup calculation, the launch flop is triggered by 1st edge and capture flop is triggered by next edge. And in calculation we take jitter into account only for the clock path of capture flop. There ...
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Does the Black's equation work for immortal wires / interconnections (or only for mortal ones)?
I'm trying to understand whether the Black's equation is only true for mortal wire / interconnections or it is also applicable to immortal wires (essentially when its \$jL\$ product is less than \$jL_{...
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Specific, practical examples of limits of logic gate fan-in?
I've been looking around for discrete, specific, and practical answers to the question "how many inputs can a (N)AND/(N)OR gate have?" as it relates to ASIC/VLSI/MOSFET/semiconductor ...
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Calculate Acitivity Factor in VLSI
Here is the problem:
And this is my solution: activity factor = probility output node is 1 x (1 - probility output node is 1)
Source: E., W.N.H. and Harris, D.M. (2011) CMOS VLSI Design: A circuits ...
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Why does Backside Power Distribution work for high speed CPUs?
Several upcoming or future CMOS process nodes are said to offer some kind of backside power delivery for Silicon CMOS transistors, so the precious area in the lower metal layers is freed up for signal ...
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Can we calculate leakage power after synthesis at the architectural level power analysis itself?
As I understand it, leakage power depends after implementation and not on the architectural level itself.
When I report power after synthesis in Vivado I get even the leakage power. Is this possible ...
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Why AND-Latch based clock gate (ICG cell) is not reliable only when driving negative edge triggered FFs?
I'm reading the paper "A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability"
https://ieeexplore.ieee.org/document/8702507
It says that with AND-Latch based ICG there could ...
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what triggers the PREADY signal in a slave of an APB?
I was trying to understand the state machine of an APB. I was curious on how the PREADY signal is triggered low so that it can exit from the ACCESS state?
If anyone could help me with this basic ...
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Latch-Up in CMOS Design
I am currently stock on a concept I should understand but I cannot get my head around it quite yet: "Latch-up" in CMOS devices. It is a condition where a significant amount of current flows through ...
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problem with CPLD and 24C16 EEPROM interface
Can any one say if it is possible to implement this code in ATMEL 24C16 EEPROM device for write the data. While I am implementing this with CPLD xc9572 I/O Pin declared as sda, scl there won't have ...
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Will the saturation current through one of these NMOS circuits always be greater than the other?
Is there a definitive way to know for all cases if an NMOS would have a greater saturation current if a resistor R is connected to 1) the drain side or 2) the source side?
The assumption is that the ...
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