All Questions
73
questions
1
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2
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113
views
Why simulation of single NMOS/PMOS on LTspice has big difference with manual calculation using Level 1 Standard Parameters?
I am researching the mode of operation on PMOS and NMOS using Level 1 standard parameters.
This is the information of the NMOS circuit to be designed.
Using transistor model level 1 parameters, ...
- 41
0
votes
1
answer
58
views
A question about layout: How to connect the gate to metal 1 layer?
I'm trying to draw a NMOS as shown above, but have some problems (the figure is from Razavi's book, the green box I added represents the N implant layer)
In the process I used, there's a design rule ...
- 625
1
vote
0
answers
76
views
Calculate Acitivity Factor in VLSI
Here is the problem:
And this is my solution: activity factor = probility output node is 1 x (1 - probility output node is 1)
Source: E., W.N.H. and Harris, D.M. (2011) CMOS VLSI Design: A circuits ...
- 401
0
votes
0
answers
100
views
Why does input threshold occur at the unique voltage at which both inverter MOSFETs are in saturation?
A relevant figure of merit for a CMOS inverter is the so-called input threshold voltage (no relationship to the threshold voltage of a given MOSFET) \$V_{inv}\$, defined as the voltage \$V_{in}\$ at ...
- 1,161
0
votes
1
answer
532
views
What is the purpose of design rules in VLSI
My doubt is what does it means micron and lamba design rules? And does it have any connections with nanometer process (eg. 7nm,14nm on microprocessor).
Actually what is the purpose of these design ...
- 75
3
votes
1
answer
343
views
Which type of mosfet used to make CMOS inverter?
My doubt is which type of mosfet used to make CMOS inverter Enhancement or depletion ?
- 75
0
votes
0
answers
26
views
How is the propagation delay of a CMOS inverter proportional to the time constant of the output capacitance? [duplicate]
I was reading a book on VLSI design and came across a chapter explaining the working of a CMOS inverter. A part of the chapter describes how the time it takes to switch between high to low or low to ...
- 9
0
votes
1
answer
1k
views
Calculating CMOS threshold voltage
I found this solution in a textbook, and I do not understand how they calculated Vth2 (typo written as 'Vth' at the bottom).
More specifically, where does the 2Vm come from?
I understand that Ids1 = ...
- 868
0
votes
1
answer
90
views
Is it possible to design dynamic logic using pre-discharge NMOS transistor and evaluation done using PMOS?
Traditionally dynamic logic has a clock input which determines whether the device will work in pre-charge or evaluation phase. PMOS is used as the pre-charge transistor and evaluation is done using ...
- 3
3
votes
4
answers
3k
views
How do processor transistor counts keep increasing, without geometric scaling?
Reading into the history of the semiconductor industry and Moore's Law, and looking at the ITRS/IRDS documents, I understand that scaling down and modern node names (7nm, 5nm etc) are now "...
- 31
0
votes
1
answer
742
views
The unusable state of S-R Latch simulation in LTSpice
I created an S-R Latch in spice using MOS transistors (180nm) and gave noth S and R inputs as 1 (knowing that this state is unusable as both Q and Qbar will be metastable). But I was expecting ...
- 178
0
votes
1
answer
819
views
Plotting MOS resistances in transmission gates in spice
I am trying to plot the resistance of MOS transistors in transmission gates, as a function of output voltage in ltSpice, as shown in this figure from Jan.M.Rabey:
I have a circuit with same ...
- 178
0
votes
1
answer
121
views
MOSFET I/V characteristics. How does this mosfet conduct current?
I am currently studying the basics of CMOS design and came across the following problem in Razavi's textbook with respect to a NMOS transistor :
The question is simple:
Let \$V_{SB}\$ = 0 (source-...
- 1,214
-1
votes
1
answer
354
views
How do the dimensions of a MOS tranistor affect the gain of a CMOS inverter?
I am simulating the voltage transfer characteristic curve of a CMOS inverter, while varying the dimensions of L and W of MOS. Comparing the results for two scenarios, I have the following results:
...
- 178
1
vote
1
answer
330
views
Multi-input NAND gate or Multiple 2-input NAND gates (VLSI design)
I am unsure which option is best practice from those featured in the title. This is part of some VLSI coursework I am doing in Cadence and so will need to do the layout of this design as well.
For ...
- 13