All Questions
10
questions
2
votes
1
answer
240
views
Understanding the rigorous definition of hold time
Consider the attached from Weste and Harris's (WH) CMOS VLSI Design. I follow all of the discussion and definitions except for the hold time definition.
Now I am familiar with the common/heuristic ...
- 1,161
0
votes
1
answer
151
views
Why do two nonoverlapping phase completely obviate the possibility of hold time issues?
In Weste and Harris's CMOS VLSI Design, they write
In Section 10.2.5 we will see that flip-flops may experience hold-time failures if the system has too much clock skew, i.e., if one flip-flop ...
- 1,161
1
vote
1
answer
3k
views
What is the triangle symbol in circuit diagrams?
What is the triagular symbols shown in the image, is it a buffer or some kind of delay?
- 15
0
votes
1
answer
277
views
Doubt regarding static timing analysis - setup time check
I was reading J.Bhasker's STATIC TIMING ANALYSIS book. In that book, he tells that when launch flip flop launches the data & while capture flip flop is capturing data, he says that
We now ...
0
votes
1
answer
81
views
Expected output of DFF_2 if DFF_1 has hold violation
I am trying to figure out the output of flop DFF_2 when
If DFF_1 has hold violation.
My answer - DFF_2(Q) = X
If DFF_2 has hold violation.
My answer - DFF_2(Q) = X
I understand the FF's go to meta-...
- 3
0
votes
1
answer
212
views
Setup and hold in flipflops
Usually the data launched at 1st clock edge will be captured at 2nd clock edge. But Is it possible to launch at 1st edge and capture data in same clock edge?
The clock to capture flip flop is delayed ...
- 101
0
votes
1
answer
5k
views
D flip-flop in Cadence
I am designing a D flip-flop. While doing my pre-layout simulations, I wasn't getting the output Q for the inputs, see attachments.
But when I tried to take the output from CLKPULSE, I was getting ...
1
vote
1
answer
2k
views
Master-Slave D-FF vs Edge triggered: timing issues, simulation shoot-through
There is a thing that bugs me about flipflops: usually, the edge-triggered flops are used, which sample D and update their Q on the posedge, i.e. master latch has inverted clock and slave latch has ...
- 682
6
votes
1
answer
931
views
Latches and Two Phase Clocking in modern ASICs
Why are latches and 2 phase clocking schemes frowned upon in modern high speed ASIC design? I understand that single edge flip-flop based designs are easier on STA tools but are there any other good ...
user105000
0
votes
1
answer
798
views
What will the output of filp-flop if its input is metastable?
I was reading sunburst paper on Clock Domain Crossing and got stuck with this doubt.
Here in the 3rd flip flop, input is metastable state but at the rising edge of the clock output was set to high. ...
- 3,192