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Questions tagged [drc]

Design Rule Check(s): a checking procedure that PCB CAD software does against a design rule file.

0 votes
1 answer
59 views

KiCad - error while building a circuit with Arduino controlling a stepper motors using XT60 connector

I am learning KiCad, and I am getting this error while building a circuit with Arduino, which control stepper motors using XT60 connector, buck converter:
Tilak Kuntalkumar Kamani's user avatar
0 votes
1 answer
72 views

Saw tooth orange sign appears when connecting wire to a component pin

I see in my schematic that when I connect a wire to a component pin a saw tooth orange sign appears on the pin: Does this representing an error? and how can remove it?(Nets containing floating input ...
Andromeda's user avatar
  • 657
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0 answers
48 views

Design rule error

I just made a PCB and updated the component form schematic to PCB:I even did not do any routing, but as you can see for two of the components (U4-U5-U3-U1-U2) I get some errors, what is the reason and ...
Andromeda's user avatar
  • 657
1 vote
1 answer
42 views

How to I set DRC rules for a specific BGA component?

I need to set the DRC rules for a BGA component. That's because JLCPCB have unique capabilities for BGA packages. In this case I need to have a unique clearance for my BGA component. I want to have ...
euraad's user avatar
  • 1,324
0 votes
1 answer
39 views

Altium designer DRC Configuration

In my schematic, I have jumpers to separate the power of an IC from the supply rails as follows: I have many of these jumpers in my circuit, when I run DRC, it says all the Vn net should be connected ...
Andromeda's user avatar
  • 657
0 votes
1 answer
58 views

A question about layout: How to connect the gate to metal 1 layer?

I'm trying to draw a NMOS as shown above, but have some problems (the figure is from Razavi's book, the green box I added represents the N implant layer) In the process I used, there's a design rule ...
Jack Black's user avatar
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0 answers
21 views

How to tune in the right DRC rule for BGA footprint - Altium CircuitMaker

According to JLCPCB, they write that their capability for the clearance between SMD pad and track is 0.2mm. 0.2mm is 7.87401575mil. If we look at a GBA processor with 0.8mm pitch. Due to the 0.2mm ...
euraad's user avatar
  • 1,324
0 votes
0 answers
107 views

Out of Board error - DRC Altium Designer

I can understand the error as some design objects are out of the boards defined bounds. Is this error a very general notification informing the designer that the whole PCB is to be reviewed and other ...
9_daytona's user avatar
1 vote
2 answers
77 views

Altium Designer 24 DRC error symbols meaning

I was wondering if anyone could help me understanding the DRC Net Antennae: via errors that look like lollipops. I've read that the double lines are related to un-routed net constraints.
9_daytona's user avatar
1 vote
1 answer
117 views

How to create in Kicad pads with different diameter on top and bottom

This is for a two layer design using Kicad 7. I need to create a footprint with 4 circular PTH pads that have larger diameter on the bottom layer than on the top layer. This is to satisfy mechanical ...
zapta's user avatar
  • 21
0 votes
1 answer
110 views

Clearence constraint between two pads of the same component, how to remove this type of error

In this Altium, the component footprint is giving a DRC error. I changed the clarity constraint parameters, but this still shows an error. This is the same case with all the components. The error is ...
Piyush's user avatar
  • 11
0 votes
1 answer
127 views

Altium Designer 23 DRC Rule Creation: How do I set a special clearance rule for a TH Pad to SMD pad?

My issue: Because of wave and selective soldering techniques, I need an 8mm clearance for an SMD pad to a TH pad that is on the opposite side of a placed TH part. Here is the scenario to better ...
Experiment-626's user avatar
0 votes
1 answer
44 views

Ground Relief Gap Design Rule -- Altium

Does anyone know of a way to implement a design rule in altium to check for instances where signals cross over a via relief ground plane gap? Example shown below. Thanks!
FooAnon's user avatar
  • 172
0 votes
2 answers
79 views

Clearance error on pin header solder pads in Eagle

I am getting a clearance error on the Sullins connector PPTC191LFBN-RC. I got the EDA models from Octopart. On including this model in my design I am getting a solder pad clearance error on both the ...
Soham Chakraborty's user avatar
2 votes
2 answers
247 views

Kicad DRC Error "Footprint has no courtyard defined"

At the final stage of the PCB design, I performed an ERC check. I got the message: Footprint has no courtyard defined @(156,718mm, 78,296mm): Footprint RV1 on Front ...
user1584421's user avatar
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