Questions tagged [physical-design]
This can refer to the design of the actual transistors inside an IC. That is also called IC layout.
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Non-ideal active low pass filter for LV25P output
Hello everyone I need some help understanding the active low-pass filter below.
I was told to use this circuit to filter the measurements of the output voltage of an inverter, but there is no ...
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In vlsi physical design ,what are the concepts to check for high standard cell growth?
What are the different checks that are usually done when there is a high standard cell growth from one stage to the next.
Eg: from place to CTS of there is a high standard cell growth what could be ...
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Multi-Cell LiOn Charging Station Safety Considerations?
I am designing a 20 cell LiOn charging station (20 cells per circuit board).
I am curious if anyone has designed such a solution and the type of enclosure you used (plastic enclosure, metal, etc)?
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Why do we alternate directions between metal layers?
In their CMOS VLSI Design and in the context of a discussion about the initial stages of floorplanning/physical design, Weste and Harris write that
Another important decision during floorplanning is ...
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How does a boogie board/LCD writing tablet/ChLCD reset actually work?
there are those boogie boards, which essentially are just special LCD screens: ChLCD screens.
which work by reflecting light on the places where it is activated.
in a boogie board, the pressure causes ...
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What's the point of memory compilers like OpenRAM or Synopsys Memory Compiler?
I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial ...
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Any spec detailing physical properties (length, area, shape) and sillicon dopping concentration of standard NPN transistors such as BC 107?
I'm trying to find the physical constructive parameters (especially doping levels) of the common NPN transistor BC 107/108/109 but I can't find any resource detailing this things, only the standard ...
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What are the theoretical constraints that prevent making the propagation delay of a CMOS inverter arbitrarily small?
I'm taking a course on CMOS circuit design and, from my course slides, I have that the the low-high propagation delay of a matched CMOS inverter is given by
$$
\frac{2\,L\,{\left(C_{\textrm{DB2}} +C_W ...
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How can standard cells of a process design kit have multi-Vdd?
I was confused after reading the datasheet of a process design kit (PDK) where it says that the standard cells support multi Vdd.
How is this possible? Isn't Vdd fixed for standard cells? Since all ...
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What's wrong with this CMOS implementation of XOR?
I'm working on a problem from an ETH Zurich course. They want you to build a transistor-level CMOS implementation of a XOR gate. My first attempt had floating nodes and other issues with untethered ...
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Why is this CMOS implementation of XOR wrong?
I'm working on a problem from an ETH Zurich course. They want you to build a transistor-level CMOS implementation of a XOR gate.
My attempt at this is the following:
The given answer is this:
Why is ...
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Standard cell design flow in an ASIC design flow
I have a question regarding the standard cell design flow in an ASIC design flow.
That being said I understand what a gate array design flow is. It being more or less a fixed logic FPGA. Structured ...
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Why is the output voltage of an electric generator limited to 25 kV?
I'm currently studying electrical machines, and reading the book I found the following statement:
The output voltage of an electric generator is usually limited to 25 kV due to physical ...
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How do I improve a simple home-made capacitor?
I was explaining to my son that a capacitor is simply 2 sheets of foil separated by a dielectric and rolled up and he said, "can we make one then?"
I'm giving it a go. I used household ...
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Variation in Tphl of MOS nand gate due to input patterns
I was studying the variation of propagation delays in CMOS NAND gate from Jan.M.Rabey Digital IC Design book. It has this table given for Tplh and Tphl for different input patterns applied at inputs A ...
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