All Questions
Tagged with vlsi chip-design
10
questions
15
votes
1
answer
2k
views
What is the standard procedure for analogue IC tapeout?
This is probably a very broad question and I will try to be more specific. I'm asking this question to get a sense of the gap between my knowledge and a 'successful' tapeout, as I've heard many people ...
0
votes
1
answer
51
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Capacitances for inverter delay calculations
In CMOS VLSI DESIGN, Neil WESTE, page 144.
"The source-to-body capacitors Csbn1 and Csbp1 have both terminals tied to constant voltages and thus do not contribute to the switching capacitance. It ...
0
votes
1
answer
510
views
Why is it necessary that the poly line extends the diffusion strip in a layout?
Here the poly ends exactly at the diffusion without clearing it, why is this a "catastrophic error" ? I understand that the transistor would never turn off if the poly only partially ...
3
votes
2
answers
4k
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Which software is used to design (and simulate) IC?
Currently I'm using Proteus to design and simulate all of my schematics. Is there any (free) software for designing and simulating ICs? I searched the Internet and found Cadence and Glade Thanks!
1
vote
2
answers
880
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Do I need to make a timing report for min/max at Static Timing Analysis in Four categories of timing paths?
I've been studying to understand Static Timing Analysis aka STA.
One of what I can't understand is whether I need to make a report timing for min/max at Static Timing Analysis in Four categories of ...
5
votes
1
answer
803
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Why are photomasks so expensive?
I just read the answer to this question asking how much a custom ASIC costs. It says that
When it comes to making an ASIC, the cost of the masks is HUGE. It is not uncommon at all for a set of masks (...
0
votes
2
answers
2k
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What is standard about standard cells in layout designing? [closed]
Why are standard cells called 'standard' cells? Why couldn't it be just cells? What is Standard about them? (I'm talking about the common terminology used in layout designing wherein the standard ...
0
votes
3
answers
542
views
Design of 7400 Series IC
Why is pin number 7 GND and 14 VCC in 7400 ICs ( logic gate ICs) ? Could the designer have put VCC and GND in some other pin number? Is there a constraint for that specific number? (Except a few cases,...
1
vote
4
answers
324
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Is there an "additive manufacturing" method to make an ASIC?
Reading questions like this one "How much does it cost to have a custom ASIC made?", I was wondering if there's some sort of equivalent to additive manufacturing that would lower the cost to getting ...
4
votes
2
answers
270
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Kick-off Spread Spectrum Clocking
Need of SSC:
Spread spectrum clocking (SSC) is a special way to reduce the radiated emissions of digital clock signals. These levels or energy is radiated and therefore this is where a potential EMI ...