All Questions
8
questions
0
votes
1
answer
58
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A question about layout: How to connect the gate to metal 1 layer?
I'm trying to draw a NMOS as shown above, but have some problems (the figure is from Razavi's book, the green box I added represents the N implant layer)
In the process I used, there's a design rule ...
- 625
2
votes
2
answers
433
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What is wrong with this XOR gate layout?
I am learning how to make layout for various CMOS gates in MAGIC. I tried to make layout for a 2 input XOR gate in MAGIC. To the best of my knowledge it should work fine when extracted to SPICE. But ...
- 505
1
vote
0
answers
46
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Why does Backside Power Distribution work for high speed CPUs?
Several upcoming or future CMOS process nodes are said to offer some kind of backside power delivery for Silicon CMOS transistors, so the precious area in the lower metal layers is freed up for signal ...
- 22.5k
0
votes
2
answers
178
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What tool produces this type of layout?
I don't under this layout figure (5.c) in pic attached.
This is a screenshot from research paper in this link:-
https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7573442
Alternate link for the ...
- 484
0
votes
1
answer
623
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Machine learning for floorplanning
I have an educational assignment to make an floor-planning tool.
Can I use machine learning in some part of the algorithm? For example, I was reading the book Algorithms for VLSI Physical Design ...
- 153
1
vote
1
answer
1k
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Why use more than one contact in VLSI layout?
I saw the following layout in one of the standard cell library provided to us by the University. In the layout, the yellow color diffusion layer is connected to blue color horizontal M1 metal layer ...
- 793
0
votes
2
answers
2k
views
What is standard about standard cells in layout designing? [closed]
Why are standard cells called 'standard' cells? Why couldn't it be just cells? What is Standard about them? (I'm talking about the common terminology used in layout designing wherein the standard ...
- 1
0
votes
1
answer
453
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Layout and Capacitance of 24/12 Inverter
Consider below layout:
It is from CMOS VLSI Design Book by West-Harris.
Why it is called 24/12 lambda inverter? I could not estimate its width/length so it match 24 and 12.
Why its capacitance is 9 ...
- 412