All Questions
Tagged with vlsi physical-design
11
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In vlsi physical design ,what are the concepts to check for high standard cell growth?
What are the different checks that are usually done when there is a high standard cell growth from one stage to the next.
Eg: from place to CTS of there is a high standard cell growth what could be ...
- 111
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2
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435
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Why do we alternate directions between metal layers?
In their CMOS VLSI Design and in the context of a discussion about the initial stages of floorplanning/physical design, Weste and Harris write that
Another important decision during floorplanning is ...
- 1,161
2
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1
answer
2k
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Uncertainty(jitter) in setup and hold calculation
In setup calculation, the launch flop is triggered by 1st edge and capture flop is triggered by next edge. And in calculation we take jitter into account only for the clock path of capture flop. There ...
- 101
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1
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623
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Machine learning for floorplanning
I have an educational assignment to make an floor-planning tool.
Can I use machine learning in some part of the algorithm? For example, I was reading the book Algorithms for VLSI Physical Design ...
- 153
2
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4
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8k
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Floorplanning vs Placement in VLSI
The major steps of physical design that I learnt from a VLSI lecture are: 1)Partitioning 2)Floorplanning 3)Placement 4)Routing. The question of mine is about the steps 2 and 3.
It seems like the ...
- 359
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2
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2k
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What is standard about standard cells in layout designing? [closed]
Why are standard cells called 'standard' cells? Why couldn't it be just cells? What is Standard about them? (I'm talking about the common terminology used in layout designing wherein the standard ...
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1
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1
answer
840
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Calculating resistance for metal layer from LEF File
I have a .LEF File which has various metals description and their parasitics information. I am trying to calculate R. It is specified as RPERSQ = 0.278.
In the File description it is written as ...
4
votes
2
answers
270
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Kick-off Spread Spectrum Clocking
Need of SSC:
Spread spectrum clocking (SSC) is a special way to reduce the radiated emissions of digital clock signals. These levels or energy is radiated and therefore this is where a potential EMI ...
- 697
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1
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331
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Clock nets Routing
We know that the clock tree synthesis is performed before signal routing. What is the specific reason for that. Or we can route both at the same time?
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3
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2
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17k
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Please explain tech.lef , tech.lib
Can anyone explain what is in the tech.lef and tech lib files? Which stage of PNR (Place and Route) are they used for? Are ...
- 51
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132
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Does the Black's equation work for immortal wires / interconnections (or only for mortal ones)?
I'm trying to understand whether the Black's equation is only true for mortal wire / interconnections or it is also applicable to immortal wires (essentially when its \$jL\$ product is less than \$jL_{...
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