All Questions
27
questions
1
vote
1
answer
406
views
Measuring the number of pulses and updating the counter after a certain number of pulses have occured using Verilog
I am trying to build a counter using Verilog which will update itself after a certain number of pulses have been detected. For example, if I am giving a 10kHz input, after every 10 pulses have been ...
2
votes
2
answers
711
views
What can procedural statements do that assignment statements cannot do in Verilog?
It seems to me that for combinational circuits assignment statements are much better and for sequential as well we can use if(clk) to run programs up to an extent, so what significant advantage does ...
- 61
0
votes
1
answer
769
views
Capture register value at specific instance in Verilog
I created two always blocks in Verilog. In one always block, one bit register variable is flipping and in other always block, a counter variable is running. Now when counter will reach to a specific ...
0
votes
2
answers
4k
views
Why do we declare the inputs of our design as reg in testbench and outputs as wire?
Why do we declare the inputs of our design as reg in testbench and outputs as wire?
- 63
2
votes
2
answers
577
views
Demo of designing a modern CPU in Verilog/VHDL [closed]
Please help me understand how such huge and complex devices like modern CPUs' are designed - would it be possible to see an example of some final circuit with billions of transistors made with Verilog/...
- 123
1
vote
2
answers
216
views
Efficient single cycle huffman decoding technique with wider input data?
I have a wider input data (Byte width) running in my system, and I'm implementing a huffman decoding on this incoming data. Since, the Huffman encoded words don't have the fixed length, hence I need ...
- 185
0
votes
2
answers
126
views
I am trying to instantiate few modules to work in top level design, but even though there is no error but I am not getting proper output
This is my verilog code. Though I am not getting any output, if any two of the instantiated modules are commented then I am getting proper partial output(For full output I need all of them to work). ...
- 31
0
votes
1
answer
169
views
Logic Synthesizer generates bad timings
I have a verilog code that describes a simple RAM. I use Genus synthesis tool to do synthesis, then generate a .sdf file for post-synth simulation. However, The tool generates .sdf file with faulty ...
- 143
1
vote
3
answers
134
views
Use condition from one clock with registers from another, synchronized clock
Is it permissible to use a condition generated by one clock with another, fully-synchronized clock (generated by a PLL with 0 phase shift) of different frequency?
This works as expected in simulation:...
- 1,063
2
votes
2
answers
2k
views
Verilog code to drive a signal high always
I am learning Verilog fundamentals recently. I want to drive a signal always high using reg. I wrote this and it didn't work.
...
- 2,772
0
votes
2
answers
2k
views
Single Clock FIFO with Single Port RAM
I wanted to make use of a single port RAM to be a single clock FIFO in verilog for an asic project , due to some constraints i can not use the dual port RAM. My confusion is when I have to perform ...
-1
votes
1
answer
144
views
SvS for Verilog
which is the best possible way to perform Schematic vs Schematic for 2 Verilog gate-level codes?
I want to do Svs just like people do for LvL in case of layout vs layout.
SvS is also available for ...
- 275
0
votes
1
answer
776
views
Does this Verilog code infer a latch?
I wrote down these lines intentionally avoiding to reset the output o when rstb is asserted:
...
3
votes
2
answers
769
views
Clock Domain Crossing: Is it possible to design an architecture from faster to slower domain and slower to faster domain simultaneously?
If I have a design which has read clock and write clock, and I want to make it work for the following scenarios:
faster read clock and slower write clock
slower read clock and faster write clock
Is ...
- 239
1
vote
1
answer
2k
views
Why is de-assertion of an asychronous reset a problem compared to its assertion?
"The biggest problem with asynchronous resets is that they are asynchronous, both at the assertion and at the de-assertion of the reset. The assertion is a non issue, the de-assertion is the issue. If ...
- 137