All Questions
22
questions
0
votes
1
answer
90
views
Question about shortest-path algorithm during synchronous circuit synthesis
In Retiming synchronous circuitry , why put a negative sign to d(u) in step 1 ? Why there is no subtraction operation for W(u, v)...
- 413
0
votes
1
answer
769
views
Capture register value at specific instance in Verilog
I created two always blocks in Verilog. In one always block, one bit register variable is flipping and in other always block, a counter variable is running. Now when counter will reach to a specific ...
2
votes
0
answers
269
views
Confusion about time borrowing
After studying timing analyzing in FPGA I still have some confusions about time borrowing like the following:
I have seen some of this site EE having good reputation saying that time borrowing is ...
- 76
1
vote
2
answers
216
views
Efficient single cycle huffman decoding technique with wider input data?
I have a wider input data (Byte width) running in my system, and I'm implementing a huffman decoding on this incoming data. Since, the Huffman encoded words don't have the fixed length, hence I need ...
- 185
0
votes
2
answers
126
views
I am trying to instantiate few modules to work in top level design, but even though there is no error but I am not getting proper output
This is my verilog code. Though I am not getting any output, if any two of the instantiated modules are commented then I am getting proper partial output(For full output I need all of them to work). ...
- 31
0
votes
1
answer
75
views
How do I approximate number of calculations/operations/memory/hardware is required for a 2^18 point FFT on chip?
I am looking for FFT implementation on Chip/FPGA. I need a high-resolution FFT which is a minimum of 2^18 points. However, I need to approximate how much hardware will I require for this process.
I ...
2
votes
1
answer
565
views
Application of set_clock_latency
I am learning about VLSI static timing analysis (STA) and some applications of SDC commands. I'm probably still missing some big picture concepts, but my question is about "why" when it comes to using ...
- 705
0
votes
1
answer
243
views
Respecting setup/hold time in RTL design
This question might sound obvious for some, however, I found that I need to understand some VLSI fundamentals.
In Functional simulation setup and hold time are equal to zero, so we can simulate the ...
1
vote
2
answers
1k
views
Edge aligned Source synchronous outputs
This is a basic block diagram of source synchronous interface I found in altera document.
Here
This is how edge aligned source synchronous output looks like.
They say the reciever will shift the ...
- 2,772
3
votes
1
answer
2k
views
Use of clock in SDC style IO constraints for FPGAs
Question on use of clock in SDC style IO delay constraints
The intention of this write up is to cast some clarity on how an FPGA IO interface has to be constrained. As a preamble the two timing ...
- 53
5
votes
6
answers
2k
views
Asynchronous Resets
I am designing an FPGA that will include state machines and counters both of which needs to be reset, I have heard that it was always better to use synchronous resets, is it true?
I am not sure that ...
- 119
3
votes
1
answer
704
views
Timing Constraints
I need to sample 24-bit data on a DAC at 25 MHz. The data comes from a design, I implemented on FPGA. In every clock cycle, the FPGA outputs a 24-bit data, which the DAC has to sample in the next ...
- 11k
7
votes
1
answer
15k
views
Get_ports vs Get_pins vs Get_nets vs Get_registers
I am doing a design in vhdl for FPGA. I have a top level design which consists of 3 components: clock divider, Module_1 and Module_2. Top level entity has a clock input port. This clock is divided by ...
- 11k
0
votes
0
answers
263
views
What is the best design practice to view multiple clocks that are generated from a single PLL within an FPGA?
Assume we have two clocks of 100 mhz and 200 mhz both generated from a PLL within an FPGA. If they are seen as two independent clock domains, then everything should work fine in the design, but there ...
- 33
0
votes
2
answers
746
views
Overlapping clock and data edges in multiple state machine designs
I have a general question about multiple state machine logic designs.
Think of a system having multiple finite state machines with a single clock and rising edged flip flops. These machines share ...
- 359