Questions tagged [synchronization]
Synchronization is the coordination of events to operate a system in unison. In digital systems this is usually accomplished by using a clock signal. (From: Wikipedia)
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What is the best approach to switching heavy loads with parallel MOSFETs?
I am going to build a spot welder with 20 MOSFETs in parallel (datasheet), each one capable of delivering 550A (1.2 kA peak approx.) powered by 35 mm2 cables connected to a 60 Ah 12 V car battery. In ...
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What is the purpose of this R-C snubber in the synchronizing cabinet?
I have an R-C snubber in the sync cabinet, which is causing me problems. When the Switch is set to a sync position on any offline generator the voltage on A phase of the generator PT's drops 3 VAC ...
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Synchronizing multiple ECUs
Say I have an ECU that controls the exterior LED lighting of a building, for aesthetic purposes. Due to the size of the building and the amount of LED strips needed, multiple ECUs are needed, each ...
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How do I implement a simple axistream by my self bus in VHDL?
I'm working on a design right now but I'm struggling with the axistream bus. I just want to be sure that I'm understanding well how it works. To do so I'm using the uvvm library to do a generator that ...
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How does a hydroturbine induction generator control its own frequency/water flow if it is already excited/pre-determined by the grid?
I was reading this article How do you connect hydro to the grid? and the author states there are two methods. One by a fixed-speed induction generator and another by a grid-tied inverter. I understand ...
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How does the second flip-flop in a naive synchronizer "prevent a metastable state from propagating"?
In this very nice answer it's explained that, fundamentally, a two flip-flop synchronizer's basic operation is to prevent the propagation of a metastable state (effectively, an invalid logic level) ...
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10MHz reference vs 1 PPS vs GPSDO
In the context of Software defined radios (SDRs), what are the differences between using an external 10MHz reference versus using a GPSDO? Why/when would you use one over the other? And how does the ...
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Pulse-per-second (PPS) Interface to FPGA
I am currently working with RFSoC 4x2 boards to implement a network of SDRs and require synchronization across multiple boards to a time reference. I plan to utilize the pulse-per-second (PPS) signal ...
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How can I emulate the signal sent by a PC sync cable to a Flash from an embedded computing board?
I have a speedlight multispectral flash (KV-FL1) with a PC sync cable that essentially sends an electrical signal when a camera's shutter opens to tell it to fire. PC sync is a Prontour-Compour ...
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Series thyristor circuit
I want to build a pulsed energy source and consider up to 6 kV for the storage capacitor voltage. The application is similar to a defibrillator but not for medical purposes. So any insights into what ...
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Genlock Analog Video
I am currently converting an TMDS signal into composite. Please see block diagram. The video encoder outputs the H-Sync and V-sync. I am also getting an external sync source that I need to use to ...
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Synchronizing signal generators with shared LO
I'm currently trying to test my ADC chip using two signal generators. Below figure visually illustrates how the test setup would look like:
The traditional approach uses a 10 MHz reference port to ...
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Building an PTP TSU + RTC module
I want to build a simple Precision Time Protocol Timestamp Unit and Real-Time clock (PTP TSU + RTC module). My accuracy requirement is +-50ns.
I found a good opencore ha1588 which fits for RTL part.
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How computers put signals in order (handling memory (system bus) access in multi-core system)?
My journey started from the question: "If I have 2 cores that want to write values in one memory address at the same (literally) time, how does a computer manage such a situation?"
After ...
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Shared FIFO control module between UART, PS/2 protocol, UART is ok, PS/2 has issue locking on to packets during read
I have brought over a design from a previously provided source in my FPGA. This is the FIFO controller for my system that gets instantiated in both UART sub system, as well as PS/2 sub system. The ...
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