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6 votes
2 answers
749 views

How to decide sizes for transistors in a design? What does it mean to design an IC?

I have recently started designing analog ICs as part of my academic work. So far all I do is take topologies given in textbooks or papers and try to design them in the PDKs available at my university. ...
Koustubh Jain's user avatar
0 votes
0 answers
23 views

Clock feedthrough of the bootstrapped switch

I'm learning about the bootstrapped switch through this paper. Razavi used a 20 µm / 28 nm NMOS (M1) as the main switch to achieve low Ron. I am wondering does this wide device cause any problem ...
Jack Black's user avatar
0 votes
1 answer
43 views

How does analog IC benefit from channel length shrinking?

I have some experience in OTA design for both 180 nm and 130 nm technologies. I didn't see much advantage of using 130 nm, as I had to use quite long channel length to achieve an acceptable gain in ...
Jack Black's user avatar
15 votes
1 answer
2k views

What is the standard procedure for analogue IC tapeout?

This is probably a very broad question and I will try to be more specific. I'm asking this question to get a sense of the gap between my knowledge and a 'successful' tapeout, as I've heard many people ...
Jack Black's user avatar
2 votes
0 answers
124 views

RHP pole of two stage OTA

I learnt that for any amplifier (with some capacitor) if we short/open the capacitor and the polarity of gain changes, it is a sign of RHP zero. Now, while applying the same analysis I obsevred that ...
sumita sahu's user avatar
6 votes
4 answers
2k views

Slew rate of two stage OTA

I have learnt two stage opamp designing from books and yourtube videos, but have always failed to understand slew rate formula which is I5/Cc(I5 is bias current of M5 and Cc is compensation capacitor)....
sumita sahu's user avatar
0 votes
5 answers
231 views

Ohm's law Vs. Ohm's relation (which one is right)?

Ok, so this might be a stupid question but I just had to ask. We are all taught that Ohm's law is: V = IR I have heard some people that insist that it should be called Ohm's relation instead of ...
Analog's user avatar
  • 399
2 votes
1 answer
462 views

How is a PMOS transistor used as a switch?

I am trying to understand switching behaviour of PMOS transistor and how exactly it passes a bad 0 value. I'm getting confused with the notation. More specifically, ...
Devesh Lohumi's user avatar
1 vote
2 answers
1k views

Zero in a basic RC high pass filter

If I write the transfer function I can clearly see a zero at zero frequency and a pole at 1/2πRC frequency. But If I simply look at this circuit I would say that there is one pole and no zero(as there ...
sumita sahu's user avatar
0 votes
0 answers
190 views

CMOS vs BiCMOS technology nodes comparison

I am trying to make a comparison between several technology nodes. More specifically I want to compare 28nm, 40nm, 65nm CMOS and BiCMOS processes. However I cannot find papers that compare some of ...
user3302780's user avatar
2 votes
2 answers
876 views

Parasitic insensitive switched capacitor circuit

I'm trying to simulate the parasitic insensitive switched capacitor circuit shown here: I am using cadence virtuoso. My input is a sine wave of 1 V amplitude, 0 DC and 1 kHz frequency. I am using ...
Sidharth Thomas's user avatar
0 votes
1 answer
197 views

Selecting Time period with multiplexer

Varying input signal I want to select delay line based on the time period of input and tap out the output of delay line to input to Multiplexer. For Example: Input Time period 1ns the input to Mux ...
Sunil Nanjiani's user avatar
1 vote
1 answer
573 views

What determines the discharge time of Dual slope ADC?

I were watching a video about dual slope ADC's here on youtube simulate this circuit – Schematic created using CircuitLab I understand that the charging equation is $$ \frac{{V_{in}}\times{t_1}...
Alper91's user avatar
  • 1,313
0 votes
1 answer
995 views

Power down current

I'm designing a Variable Gain Amplifier (VGA) for a course project. I'm using Cadence CMOS 180nm technology. One of the requirements is to find the power down current through simulation. I searched on ...
Rana Mahmoud's user avatar
2 votes
1 answer
600 views

Free spice Model to simulate integrated circuits design

I am using ltspice and I would like to simulate integrated full custom circuits for educational purpose. I found the NMOS4 and PMOS4 models but there are not enough since there are too ideal there ...
TM90's user avatar
  • 455