Questions tagged [vlsi]
VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.
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Why would an AND gate need six transistors?
I'm taking a digital design course, and I've been told that a NAND gate needs four transistors to implement and an AND gate needs six (four for a NAND gate and two for an inverter). That makes sense ...
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Why do we declare the inputs of our design as reg in testbench and outputs as wire?
Why do we declare the inputs of our design as reg in testbench and outputs as wire?
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Precise differences between DRAM and CMOS processes
There are a couple of questions that mention the difference between standard CMOS processes and DRAM manufacture:
Why do microcontrollers have so little RAM?
How do they integrate logic into a DRAM ...
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Why All 1's used as a second input in decrement operation of ALU?
Suppose the first four data inputs are X (X0, X1, X2, X3) and the second four data inputs are Y (Y0, Y1, Y2, Y3) in a 4-bit ALU. Why "All 1's" are used as an input for Y in the decrement operation of ...
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Why does decreasing the CMOS supply voltage also decrease the maximum circuit frequency?
In CMOS circuit design, we know dynamic power is proportional to \$V_{dd}^2Cf\$, so the best way to reduce dynamic power is to reduce \$V_{dd}\$.
However, according to the textbook,
Keeping the same ...
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Why does Moore Finite State Machine need more states than Mealy Finite State Machine?
I was reading about finite state machines. I read about Moore and Mealy machine and also the state representation. I read that in the Moore machine the output depends on the present state only and in ...
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Why delays cannot be synthesized in Verilog?
I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code.
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Asynchronous Resets
I am designing an FPGA that will include state machines and counters both of which needs to be reset, I have heard that it was always better to use synchronous resets, is it true?
I am not sure that ...
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Implementation of AES algorithm using Systolic architecture
I need to generate a VLSI Systolic array to implement the AES encryption algorithm with key length of 128 bits. Following are the possible ways :
Systolic for Key expansion
Systolic in MixColumn
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Random clock Generation with unequal 1s and 0s distribution?
We need a pseudo-random clock with a length N, in such a way that out of every N clock pulses, ...
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Why doesn't voltage on one terminal of a capacitor matter?
In the context of characterizing the load driven by an inverter by an effective capacitance, my textbook (CMOS VLSI Design: A Circuits and Systems Perspective, 4th edition, by Weste and Harris) gives ...
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SDC constraints for source clock and derived clock
There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1-bit data from clk1 to clk2.
I know this is a kind of asynchronous scenario and the traditional ...
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How does an aggressor raise/drop the voltage of the victim in crosstalk?
I have been trying to understand, intuitively and physically, how crosstalk works. If I have a net that is switching (from either LO to HI or from HI to LO) running adjacent to a static line (LO or HI)...
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How do you reduce an 8 output ALU to a 4 or 3 output ALU?
I can implement the functions in the picture below, but then if I implement them independently, I would have 8 outputs to the mux. Our professors wants us to reduce the ALU to only 3 or 4 outputs, I ...
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Do I need to make a timing report for min/max at Static Timing Analysis in Four categories of timing paths?
I've been studying to understand Static Timing Analysis aka STA.
One of what I can't understand is whether I need to make a report timing for min/max at Static Timing Analysis in Four categories of ...
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