All Questions
Tagged with vlsi digital-logic
61
questions
1
vote
0
answers
67
views
Specific, practical examples of limits of logic gate fan-in?
I've been looking around for discrete, specific, and practical answers to the question "how many inputs can a (N)AND/(N)OR gate have?" as it relates to ASIC/VLSI/MOSFET/semiconductor ...
-2
votes
2
answers
105
views
Why are interrupts active low? [closed]
Came across this question recently and saw some answers too, but need a simple answer which is easy to understand.
1
vote
1
answer
144
views
On DC transfer characteristics, logic levels, and the static discipline
One thing that's confused me ever since I started studying digital design is what it means when books say, roughly, that we can choose or define the input and output thresholds for a given circuit ...
- 1,161
2
votes
1
answer
240
views
Understanding the rigorous definition of hold time
Consider the attached from Weste and Harris's (WH) CMOS VLSI Design. I follow all of the discussion and definitions except for the hold time definition.
Now I am familiar with the common/heuristic ...
- 1,161
1
vote
2
answers
226
views
Why do we use a MUX rather than tristate buffers to implement a bus?
Consider a small digital system consisting of registers connected to a bus interconnection network. It is well-known that the output to the bus can (functionally) be implemented either with tristate ...
- 1,161
3
votes
1
answer
293
views
How does this logic gate naming convention work?
In their CMOS VLSI Design, Weste and Harris seem to use a naming convention for logic gates which I cannot quite seem to define in my head. Ill give the two examples they use and hopefully someone ...
- 1,161
8
votes
5
answers
1k
views
What is the difference between a tristate buffer and a transmission gate?
Functionally, these two "blocks" seem to do the same thing: send input to output if enabled and present high impedance Z on the output if not. However, this answer seems to suggest a ...
- 1,161
3
votes
1
answer
457
views
What is the propagation delay of a carry save adder?
I was reading this paper about the Comparison of Adder Topologies, when I came across a page talking about the Carry Save Adder. They say on page 3:
The propagation delay is 3 gates regardless of the ...
- 143
0
votes
1
answer
130
views
Why is the gamma term missing in the first case of single transistor example?
This is the video.
How is the gamma term present in one case and absent in another?
- 61
1
vote
0
answers
666
views
Why AND-Latch based clock gate (ICG cell) is not reliable only when driving negative edge triggered FFs?
I'm reading the paper "A Novel Glitch-Free Integrated Clock Gating Cell for High Reliability"
https://ieeexplore.ieee.org/document/8702507
It says that with AND-Latch based ICG there could ...
- 249
2
votes
2
answers
336
views
How can I design a digital circuit where the output is 5 times the input? [closed]
I tried to solve this challenge by enhancing my skills in digital circuits, but could not solve it.
How can I design a digital circuit where the input is only 2 bits and the output equals 5 times the ...
- 31
0
votes
1
answer
95
views
RDC from FF with async reset to FF with sync reset (no reset pin) - what is the design practice to solve this?
Given the below scenario, which is a reset-domain-crossing violation :
Can it be resolved using some reset synchronization strategy?
Is such design considered bad to begin with, i.e. need to avoid ...
2
votes
2
answers
711
views
What can procedural statements do that assignment statements cannot do in Verilog?
It seems to me that for combinational circuits assignment statements are much better and for sequential as well we can use if(clk) to run programs up to an extent, so what significant advantage does ...
- 61
0
votes
1
answer
90
views
Is it possible to design dynamic logic using pre-discharge NMOS transistor and evaluation done using PMOS?
Traditionally dynamic logic has a clock input which determines whether the device will work in pre-charge or evaluation phase. PMOS is used as the pre-charge transistor and evaluation is done using ...
- 3
0
votes
2
answers
754
views
How does logic 1 get passed through an NMOS pass transistor?
I'm studying pass transistors. One thing I came across in several of the books is that when an NMOS has a logic state HIGH and the input terminal (the schematic below) is also HIGH, the output ...
