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1 vote
0 answers
67 views

Specific, practical examples of limits of logic gate fan-in?

I've been looking around for discrete, specific, and practical answers to the question "how many inputs can a (N)AND/(N)OR gate have?" as it relates to ASIC/VLSI/MOSFET/semiconductor ...
Maxwell Phillips's user avatar
4 votes
2 answers
632 views

Prevent spikes during transition of inputs in AND gate

Question Suppose we have a two-input AND gate. The inputs do not change instantly. So, it's not a perfect rectangular signal rather trapezoidal. Consider the situation when input 1 is transiting to ...
Rudranath Palit's user avatar
2 votes
1 answer
2k views

Why does lowering VDD increases the delay for digital circuits?

I've preparing for Physical Design Interview and came across couple of explanations that deduce that the delay of logical gates will increase once we reduce VDD. what is the reason? my intuition sends ...
Firas Abd El Gani's user avatar
0 votes
1 answer
2k views

Calculating propagation delay for a logic circuit

Given the above combinational logic diagram, How to calculate the propagation delay? AND->OR->AND-NOT NOT->AND->NOT I see the above two longest paths. So what I understand is just take ...
puneeta's user avatar
1 vote
1 answer
69 views

How to find what circuitry is required for synthesis of following digital VLSI design problem?

My thoughts: Here price of chocolate is increasing in Geometric progression with common ratio 2 and first term 1, so on nth day price of chocolate will be $T_{n}=2^{n-1}$\ irrespective of wheather ...
MR LUN's user avatar
  • 15
0 votes
1 answer
88 views

General CMOS circuit

In any CMOS circuit like an inverter or an n-input NOR or NAND gate, where the pMOS network is connected at the top to Vdd source terminal and nMOS network is connected at the bottom to the ground ...
Sai Krishna Garlapati's user avatar
27 votes
6 answers
9k views

Why would an AND gate need six transistors?

I'm taking a digital design course, and I've been told that a NAND gate needs four transistors to implement and an AND gate needs six (four for a NAND gate and two for an inverter). That makes sense ...
Dev-XYS's user avatar
  • 381
0 votes
1 answer
439 views

Is state machine based sequence detector easier to verify than shift register based one?

Suppose I have two versions of sequence detectors: one is based on let's say Moore machine and the other one is based on simple shift register & comparator. Which one among these is easy to verify ...
pcs's user avatar
  • 1
0 votes
3 answers
542 views

Design of 7400 Series IC

Why is pin number 7 GND and 14 VCC in 7400 ICs ( logic gate ICs) ? Could the designer have put VCC and GND in some other pin number? Is there a constraint for that specific number? (Except a few cases,...
user167930's user avatar
3 votes
3 answers
998 views

Properly simulating a NAND gate? (I'm building a computer in my computer)

I am about to embark on a project, enspired by Nand2Tetris (http://www.nand2tetris.org/), to fully simulate a computer, building the entire thing up from NAND gates. I want to simulate everything ...
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