Questions tagged [vlsi]
VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.
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FD-SOI Channel formation with fully depleted body
In an FD-SOI the body is undoped, which could be just an intrinsic semiconductor such as silicon. What I'm wondering is how the channel is formed in an FD-SOI when the body isn't doped at all. My ...
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Specific, practical examples of limits of logic gate fan-in?
I've been looking around for discrete, specific, and practical answers to the question "how many inputs can a (N)AND/(N)OR gate have?" as it relates to ASIC/VLSI/MOSFET/semiconductor ...
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Clock feedthrough of the bootstrapped switch
I'm learning about the bootstrapped switch through this paper. Razavi used a 20 µm / 28 nm NMOS (M1) as the main switch to achieve low Ron. I am wondering does this wide device cause any problem ...
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How does analog IC benefit from channel length shrinking?
I have some experience in OTA design for both 180 nm and 130 nm technologies. I didn't see much advantage of using 130 nm, as I had to use quite long channel length to achieve an acceptable gain in ...
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How to implement 2 stage pre-decoding
I've been studying VLSI and I came across a design problem regarding decoders.
Let's same I want to design a 12:4096 decoder using inverters, NAND 3 and NOR4 gates. Implementing this decoder without ...
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can someone explain the working /operation of FinFET?
Any resources that give in depth analysis of FinFET working would be helpful.
I read a couple of papers on IEEE but most of them had very little information related to the working principle.
user373485
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Transistors sizing on commercial VLSI custom design projects
I have a doubt regarding the way circuits sizing is carried out in custom design style commercial projects.
For example, let consider the design of a fast adder for a high performance CPU.
At logical ...
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Why simulation of single NMOS/PMOS on LTspice has big difference with manual calculation using Level 1 Standard Parameters?
I am researching the mode of operation on PMOS and NMOS using Level 1 standard parameters.
This is the information of the NMOS circuit to be designed.
Using transistor model level 1 parameters, ...
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In vlsi physical design ,what are the concepts to check for high standard cell growth?
What are the different checks that are usually done when there is a high standard cell growth from one stage to the next.
Eg: from place to CTS of there is a high standard cell growth what could be ...
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A question about layout: How to connect the gate to metal 1 layer?
I'm trying to draw a NMOS as shown above, but have some problems (the figure is from Razavi's book, the green box I added represents the N implant layer)
In the process I used, there's a design rule ...
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What is the standard procedure for analogue IC tapeout?
This is probably a very broad question and I will try to be more specific. I'm asking this question to get a sense of the gap between my knowledge and a 'successful' tapeout, as I've heard many people ...
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Why are interrupts active low? [closed]
Came across this question recently and saw some answers too, but need a simple answer which is easy to understand.
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On DC transfer characteristics, logic levels, and the static discipline
One thing that's confused me ever since I started studying digital design is what it means when books say, roughly, that we can choose or define the input and output thresholds for a given circuit ...
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Issue in understanding routing in VLSI CAD
I have chosen to undertake VLSI CAD as a part of my electronics degree and I came across this statement (Source : Naveed Sherwani, Algorithms for VLSI Physical Design Automation, 3rd edition , Chapter ...
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How does the second flip-flop in a naive synchronizer "prevent a metastable state from propagating"?
In this very nice answer it's explained that, fundamentally, a two flip-flop synchronizer's basic operation is to prevent the propagation of a metastable state (effectively, an invalid logic level) ...
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