All Questions
12
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How is the propagation delay of a CMOS inverter proportional to the time constant of the output capacitance? [duplicate]
I was reading a book on VLSI design and came across a chapter explaining the working of a CMOS inverter. A part of the chapter describes how the time it takes to switch between high to low or low to ...
- 9
2
votes
2
answers
699
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What is meant by\$ I_{peak} \$current in CMOS inverter?
This is a snap from Chapter number 5 CMOS inverter, Digital integrated circuit by Jan M Rabaey .
I just wanted to know from where this \$I_{peak}\$ is measured. The direct path current exist till the ...
- 659
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1
answer
5k
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What is happening when I am adding a load capacitor in CMOS inverter?
I want to simulate an inverter with CMOS. When I added a load capacitance and plotted the output voltage. I saw a sharp voltage graph so I have changed the dimensions of the transistors and got the ...
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5
answers
8k
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CMOS logic Gates XOR
I'm currently doing the practice problems for CMOS VLSI Design 4th Edition. Question 1.6 says to use a combination of CMOS gates to generate the following functions (solution attached below function ...
- 169
1
vote
1
answer
175
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Logical effort and delay estimation
So as I have understood the logical effort for a 2 input nand gate with only one of the inputs active = 4/3. Furthermore the net logical effort is 8/3 (considering both the inputs). Now given that the ...
- 35
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1
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396
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What does it mean to establish the state of the internal node in CMOS circuit?
This is the NAND circuit and the 'int' is the internal node of the circuit.
It is seen that A = B= 0→ 1 gives the worst delay in the below table. What does it mean to establish the state of the ...
- 137
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1
answer
1k
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What does low-impedance mean in the CMOS inverter circuit?
For the CMOS inverter the text states "once the transients have settled, a path always exists between VDD and the output realizing a high output (“one”), or, alternatively, between VSS and output for ...
- 137
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3
answers
2k
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Why the drop across NMOS enhancement mode load is V_t when driver is off?
In the enhancement load NMOS inverter, why is the voltage drop across the Transistor \$Q_1\$ when \$Q_2\$ is off, is \$V_t\$ ?
When \$V_{1}\$ is low, the transistor \$Q_1\$ is off. For the ...
- 133
0
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1
answer
254
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falling delay inverters VLSI CMOS
How do I obtain the falling delay driving by signal A:
Data:
...
- 11
1
vote
0
answers
105
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Preference of MOS resistor as load in MOS inverter [closed]
Whys is a MOS resistor preferred over diffused resistor as load in design of a MOS inverter?
1
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3
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6k
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Why does there have to be a load in MOS inverters?
I have been studying about inverters for a while. In the book that I was reading, inverters have been explained according to the type of load connected to the drain of the driving transistors ie. ...
- 1,177
2
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1
answer
9k
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CMOS Inverter Equal Rise and Fall Times
I am currently attempting to design an inverter in Microwind layout software that has equal rise and fall times. Rise time is defined as the time for the circuit's output to go from 10 percent to 90 ...
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