All Questions
8
questions
2
votes
2
answers
1k
views
Are there MOS VLSI Process Design Kits (SPICE models) for free SPICE simulators?
I want to do some proof-of-concept work in IC analogue IC design. I know that plenty of free circuit simulators exist (LTSpce, NgSpice etc.), however they are meant for PCB simulation and most perform ...
0
votes
1
answer
623
views
Machine learning for floorplanning
I have an educational assignment to make an floor-planning tool.
Can I use machine learning in some part of the algorithm? For example, I was reading the book Algorithms for VLSI Physical Design ...
- 153
9
votes
4
answers
1k
views
What method do you suggest for prototyping asynchronous circuits?
I got surprised and to a degree shocked by finding that there is no proper established tool for designing and prototyping asynchronous circuits.
I keep searching using google and other means to find ...
- 876
2
votes
2
answers
208
views
Transistor level netlist benchmarks
I'm PhD student in CAD/EDA field. My research topic covers VLSI standard cell's layout design and detailed routing. To make my research results more reliable, I would like to test proposed algorithm ...
- 143
-1
votes
1
answer
957
views
recalculate delay from fsdb file
I came across hsim help menu and I found these two switches pretty interesting.
...
- 275
3
votes
2
answers
17k
views
Please explain tech.lef , tech.lib
Can anyone explain what is in the tech.lef and tech lib files? Which stage of PNR (Place and Route) are they used for? Are ...
- 51
2
votes
3
answers
294
views
Routing of an ASIC chip - time taken?
In a typical ASIC design cycle, how much time is taken by an EDA tool to complete the routing?
Assume a fairly complex chip (like the Ivy Bridge). I've heard the entire chip design cycle is typically ...
- 73
7
votes
4
answers
5k
views
Getting starting designing CMOS ASIC - What is the must have software?
What software should I use to design a pipeline of gates? The design will be implemented on TSMC's 350nm process. A list of must-have software to design a basic gate circuit, and ASIC solutions would ...
- 247