Questions tagged [asic]
An ASIC is an Application Specific IC. It is a custom chip that is made at the factory.
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Specific, practical examples of limits of logic gate fan-in?
I've been looking around for discrete, specific, and practical answers to the question "how many inputs can a (N)AND/(N)OR gate have?" as it relates to ASIC/VLSI/MOSFET/semiconductor ...
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Alignment characters in the JESD204B standard
I have a question regarding the alignment characters in the JESD204B data converter interface protocol.
To anyone who is familiar with this protocol. There are certain alignment that are used during ...
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Behaviour of uninitialised RAM in an ASIC
This is a question for anyone with experience designing or with a deep knowledge of volatile memory in an ASIC. E.g. chip designers or silicon process engineers.
We are using the ET1200 EtherCAT ASIC (...
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How to be sure that the SPICE simulation results are the exact results I will get when I build the circuit (especially an ASIC) in real?
I have been doing circuit simulation in HSPICE for research. The final stage of the research is to build an ASIC. The simulation results are often satisfactory. However, I am still in doubt if the ...
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The quality of testbenches with UVM testing
This thread partially answers the question that I have Writing synthesizable testbenches, but I'm still not truly satisfied.
So I come from a hardware engineering background, as I was discussing how ...
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What is the need for implementing synthesizable linked list module in RTL?
Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs.
Given that synthesized hardware has static memory size, what's the ...
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What does ‘full custom’ really mean?
It’s common in my intro digital logic/VLSI textbooks to see mention of “full custom” chips versus ASIC chips. I’m interested in understanding the difference between the two in the context where both ...
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What/why are the patterns in the "unused" portion of this ASIC?
The below image is a 150um x 170um block from an ASIC design file produced automatically by fully open-source tools such as yosys.
The apparently unused sections have a repetitive pattern, presumably ...
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How to do clock signal rising edge detection in Chisel (scala)?
I have encountered in a problem of rising edge detection in writing chisel code. Here is the code I wrote.
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Is it possible to reset SRAM in one cycle?
If you have some SRAM in an ASIC and you want to reset it to 0 quickly, rather than looping over the entire memory can you just write to all words in parallel by asserting all word lines at once (this ...
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Can we say that a CPU is an ASIC that is designed to perform a wide range of instructions?
My question is more terminological than technical.
I have come across different definitions of what an ASIC is. The most common one is that an ASIC is an IC that is designed for a specific application ...
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Can a digital system be considered an ASIC regardless its physical implementation?
From my knowledge from classical books of computational and digital systems, an ASIC is a category of full-customized or semi-customized integrated circuit (IC) tailored to a specific application.
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Are SR latches bad in ASIC design?
I am implementing an ASIC design, and my current solution for a problem requires an SR latch. I've always been told that latches are bad in FPGA and ASIC designs, but never got a proper answer as to ...
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How does the switch in this board control four different states in the LED? [closed]
I have the simplest board with a LED and a switch, powered by 2 CR2032 3V (pictures attached).
There is 4 possible states:
LED is off.
LED flashing slowly.
LED flashing fast.
LED is constantly on.
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Clock domain crossing without synchronisers
I am (re)designing an SPI slave module in VHDL for an ASIC. The SPI domain is faster than the main clock domain (~10MHz and ~1MHz), so the SPI state machine operates in the SPI domain. The previous ...
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