namely that subset of analog circuits which is such that, unless switching, all signals are near HIGH or LOW because of the nature of the subcircuits contained therein.
That's only in binary logic, and even that is inaccurate.
Ternary logic was used in the Soviet Union for some research computers, there are hobbyists actively designing such circuits (myself included).
Internal logic levels inside of the gates may have not much to do with external logic levels. Just two examples:
a logic chip may work with 3.3V I/O, but internally at say 1.8V; many MCUs do something like that,
ECL logic gates routinely used 4 or 6 logic levels internally in the chip, while externally there were only 2 levels.
Quaternary and higher radix logic is used internally in FLASH memories, such as those used in solid-state drives (SSD).
Non-binary logic is often used for data transmission.
Ternary logic is extremely common - you surely have some of it at home. 100MBit ethernet uses ternary MLT-3 line encoding
High-radix logic levels is used on the air in modems of all sorts: good old telephone modems, cable modems, cellular digital transmission, digital radio, satellite services, etc.
books say, roughly, that we can choose or define the input and output thresholds for a given circuit family. I was unsure why those were seemingly so arbitrary
Well, they are not exactly arbitrary. We choose those levels to fulfill the requirements of the logic family. When designing a logic family, we choose the operating voltage range, noise margins, architecture of the gates (TTL vs RTL vs two-level CMOS vs ECL), and so on - all with mind on the application area, manufacturability and yield constraints, available technologies vs. R&D effort, etc.
Some logic "families" are only designed for I/O purposes, i.e. you don't have any "gates" in the family, but only transceivers that talk to each other using that "family", but interface to the rest of the circuit using other logic levels entirely. LVDS (low-voltage differential signaling, as used in HDMI, superspeed USB, etc.) is a common example.
The exact levels depend on - among other things -
the architecture of the input and output circuits within each logic element (gate, FF, register, ...),
the semiconductor process used to implement said architecture, including tweaks to parameters of the individual devices on the chip (say a couple transistors use a different diffusion for the channel than the rest of the chip).
For example, you could have some high-voltage variant of bipolar ECL if the semiconductor process was high-voltage bipolar. Not that it would necessarily be useful, but if you needed it, the levels would be influenced by what the process can survive, and by how the ECL architecture fundamentally works.
Same with CMOS: the voltage rating of the CMOS process will determine the allowable range of the logic levels - they cannot exceed the supply rails usually. Within those limits, the levels will be determined by the thresholds of the MOS devices in the IC. Those device thresholds can be further tweaked e.g. by using the body effect, adjusting the process parameters, adding diffusion steps to "customize" selected transitors' behavior, choosing a particular input or output topology, ...
For example, you can design a 3.3V CMOS logic output transceiver with differential input that has input threshold at say 0V differential voltage, i.e. differential voltages <0V register as low, differential voltages >0V register as high. The common mode voltage of the differential input can be "anywhere" in the supply range. So, that logic gate, if presented with voltages 0.2V and 0.3V on the two inputs would output a high logic level, but when presented with voltages 3.2V and 0.0V would output a low logic level.
Why can we define thresholds? I have some vague sense that it's related to my two paragraphs above, but I can't quite get my arms around it.
Because logic circuits are fundamentally analog circuits. When you design a CMOS gate's input circuits, you can choose what gate-source threshold voltages the MOS devices in that input circuit have, and that determines the input logic level. How you arrange the transistors, what sort of internal reference voltage sources you use (if any), etc. It's all almost infinitely configurable. What matters in practice is whether it's useful for anything so that you can hope to get customers to buy it from you, and how manufacturable it is - production yields affect profit margins and make-or-break the profitability of a semiconductor product.
Same when you design the CMOS gate's output circuits. They may, for example, be a level translator - the input logic levels may be 0V and 3.3V, but the output logic levels may be arbitrary and defined by two input voltages. That's not hard to do. Take any 2:1 analog multiplexer. The two inputs define the output logic levels - just hook them up to constant voltages. The "select" input of the multiplexer then is the "normal" logic level input. Although CMOS output stages are not usually designed using pass gates like analog muxes are, there's nothing fundamentally that forbids that. Is is an easy way to get logic translation from HV CMOS levels (say 12V supply CD4000 logic family) to any other levels (say 0V and 1.8V).
it seems like only gates with transfer characteristics (with respect to a given input) which achieves a slope of absolute value greater than 1 can be used as a digital logic gate.
Fundamentally yes, since otherwise the gates won't be saturating the outputs, and after a few gates the logic levels will be invalid.
Although that's a simplification too. In practice, sometimes such logic elements are used internally to reduce power consumption, and interspersed are "snap action" elements that re-generate the "saturated" logic levels.
You have to be very careful about textbooks, because they make all sorts of simplifications but do an awful job explaining what those simplifications are. In almost any area of engineering, the reality is usually way more complex than the introductory textbooks would lead you to believe. The books you're talking about are certainly of an introductory character. For the state of the art, look into contemporary published research on CMOS circuits etc. It can be overwhelmingly complex if you look deep enough.
