All Questions
10
questions
3
votes
1
answer
2k
views
How to correctly constrain a clock network with lots of mux branches?
Let me simplify a common clock network structure used in my company:
Firstly, there're multiple true clock sources (PLLs, external input, or RC OSCs).
Right at the beginning when these sources are &...
- 351
1
vote
1
answer
3k
views
What is the triangle symbol in circuit diagrams?
What is the triagular symbols shown in the image, is it a buffer or some kind of delay?
- 15
0
votes
1
answer
277
views
Doubt regarding static timing analysis - setup time check
I was reading J.Bhasker's STATIC TIMING ANALYSIS book. In that book, he tells that when launch flip flop launches the data & while capture flip flop is capturing data, he says that
We now ...
1
vote
3
answers
134
views
Use condition from one clock with registers from another, synchronized clock
Is it permissible to use a condition generated by one clock with another, fully-synchronized clock (generated by a PLL with 0 phase shift) of different frequency?
This works as expected in simulation:...
- 1,063
7
votes
1
answer
15k
views
Get_ports vs Get_pins vs Get_nets vs Get_registers
I am doing a design in vhdl for FPGA. I have a top level design which consists of 3 components: clock divider, Module_1 and Module_2. Top level entity has a clock input port. This clock is divided by ...
- 11k
1
vote
1
answer
505
views
Why ring oscillator showing irregular graph ?
I'm trying to design ring oscillator in CADENCE using 180 CMOS .Instead of showing inverted clocking output , output changes in less then millivolt ranges. When I connect only 9 inverter like this ...
- 1,176
0
votes
2
answers
746
views
Overlapping clock and data edges in multiple state machine designs
I have a general question about multiple state machine logic designs.
Think of a system having multiple finite state machines with a single clock and rising edged flip flops. These machines share ...
- 359
3
votes
1
answer
768
views
Random clock Generation with unequal 1s and 0s distribution?
We need a pseudo-random clock with a length N, in such a way that out of every N clock pulses, ...
- 238
0
votes
1
answer
1k
views
Carry-lookahead adder in VLSI, Static VS Dynamic?
I study one course about VLSI. in adder lecture my profesor talk about Adders. in Carry-lookahead adder first talk about static version, as follows:
at next we start about dynamic version of CLA and ...
1
vote
1
answer
5k
views
How to create variable clock frequency source in Cadence Virtuoso?
I am working on Delay Locked loop Project. I want to check the lock range of the dll. I am using vpulse for clock but by giving parameters clock period, clock width, rising time, falling time. It ...
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