Questions tagged [vlsi]
VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.
331
questions
27
votes
6
answers
9k
views
Why would an AND gate need six transistors?
I'm taking a digital design course, and I've been told that a NAND gate needs four transistors to implement and an AND gate needs six (four for a NAND gate and two for an inverter). That makes sense ...
- 381
19
votes
4
answers
5k
views
Why aren't fully asynchronous circuits more prevalent? [closed]
From my understanding, most modern consumer CPU's are based on synchronous logic. Some high-speed applications (signal processing, etc.) use ansync logic for its higher speed.
However, in today's ...
- 301
15
votes
1
answer
2k
views
What is the standard procedure for analogue IC tapeout?
This is probably a very broad question and I will try to be more specific. I'm asking this question to get a sense of the gap between my knowledge and a 'successful' tapeout, as I've heard many people ...
- 625
12
votes
2
answers
6k
views
Are chicken bits left in space-qualified ICs?
A chicken bit "is a bit on a chip that can be used by the designer to disable one of the features of the chip if it proves faulty or negatively impacts performance."
Would space-qualified logic ...
- 409
10
votes
1
answer
3k
views
Precise differences between DRAM and CMOS processes
There are a couple of questions that mention the difference between standard CMOS processes and DRAM manufacture:
Why do microcontrollers have so little RAM?
How do they integrate logic into a DRAM ...
- 46.9k
9
votes
4
answers
1k
views
What method do you suggest for prototyping asynchronous circuits?
I got surprised and to a degree shocked by finding that there is no proper established tool for designing and prototyping asynchronous circuits.
I keep searching using google and other means to find ...
- 876
8
votes
5
answers
1k
views
What is the difference between a tristate buffer and a transmission gate?
Functionally, these two "blocks" seem to do the same thing: send input to output if enabled and present high impedance Z on the output if not. However, this answer seems to suggest a ...
- 1,161
8
votes
3
answers
8k
views
Why delays cannot be synthesized in Verilog?
I have always read that delays declared in RTL code can never be synthesized. They are meant only for simulation purpose and modern synthesis tools will just ignore delays declarations in the code.
...
- 227
7
votes
4
answers
5k
views
Getting starting designing CMOS ASIC - What is the must have software?
What software should I use to design a pipeline of gates? The design will be implemented on TSMC's 350nm process. A list of must-have software to design a basic gate circuit, and ASIC solutions would ...
- 247
7
votes
5
answers
1k
views
What determines the maximum clock rate for a CPU?
What factors determine the maximum CPU clock rate? A 6502, for instance, clocks in the megahertz range, while an Intel x64 chip typically clocks in the gigahertz range.
All things being equal, if the ...
- 2,397
7
votes
1
answer
15k
views
Get_ports vs Get_pins vs Get_nets vs Get_registers
I am doing a design in vhdl for FPGA. I have a top level design which consists of 3 components: clock divider, Module_1 and Module_2. Top level entity has a clock input port. This clock is divided by ...
- 11k
7
votes
2
answers
1k
views
How do the VLSI design rules for finFET differ from traditional MOSFET/CMOS design?
I'm taking an intro to VLSI class right now and we're learning the design rules for laying out chips on a 600 nm process. This was the state of the art in the early 90's so it should be a little out ...
- 73
6
votes
5
answers
7k
views
Can a NOT gate be used to achieve 180 degree phase shift?
I have seen from various sources which say that a NOT gate cannot be used to achieve an 180-degree phase shift. Is this claim true?
Edit: The question is definitely sounding unclear because that is ...
- 197
6
votes
4
answers
2k
views
Slew rate of two stage OTA
I have learnt two stage opamp designing from books and yourtube videos, but have always failed to understand slew rate formula which is I5/Cc(I5 is bias current of M5 and Cc is compensation capacitor)....
- 209
6
votes
2
answers
750
views
How to decide sizes for transistors in a design? What does it mean to design an IC?
I have recently started designing analog ICs as part of my academic work. So far all I do is take topologies given in textbooks or papers and try to design them in the PDKs available at my university. ...
- 505