Questions tagged [vlsi]
VLSI stands for Very Large Scale Integrated circuits, which at one time had meaning in context to the scale of integration. With the advent of modern processes with billions of transistors per design, it is used as a generic term to mean ICs in common usage.
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How to decide sizes for transistors in a design? What does it mean to design an IC?
I have recently started designing analog ICs as part of my academic work. So far all I do is take topologies given in textbooks or papers and try to design them in the PDKs available at my university. ...
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dynamic charge sharing between multiple gates
Based on this video: https://www.youtube.com/watch?v=CN4oIcAPIV4
hopefully it is legitimate
I understand what is being done here. However, I don't understand it well enough for a more complex case ...
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How to get a CMOS transistor SPICE model?
So far in order to simulate CMOS circuits I relied on a library that I had to randomly download from Internet such as this one:
http://ecee.colorado.edu/~ecen4827/spice/ltspice/5827_035.lib
Inside ...
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Specific, practical examples of limits of logic gate fan-in?
I've been looking around for discrete, specific, and practical answers to the question "how many inputs can a (N)AND/(N)OR gate have?" as it relates to ASIC/VLSI/MOSFET/semiconductor ...
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FD-SOI Channel formation with fully depleted body
In an FD-SOI the body is undoped, which could be just an intrinsic semiconductor such as silicon. What I'm wondering is how the channel is formed in an FD-SOI when the body isn't doped at all. My ...
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Clock feedthrough of the bootstrapped switch
I'm learning about the bootstrapped switch through this paper. Razavi used a 20 µm / 28 nm NMOS (M1) as the main switch to achieve low Ron. I am wondering does this wide device cause any problem ...
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How does analog IC benefit from channel length shrinking?
I have some experience in OTA design for both 180 nm and 130 nm technologies. I didn't see much advantage of using 130 nm, as I had to use quite long channel length to achieve an acceptable gain in ...
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Logic Synthesizer generates bad timings
I have a verilog code that describes a simple RAM. I use Genus synthesis tool to do synthesis, then generate a .sdf file for post-synth simulation. However, The tool generates .sdf file with faulty ...
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How to implement 2 stage pre-decoding
I've been studying VLSI and I came across a design problem regarding decoders.
Let's same I want to design a 12:4096 decoder using inverters, NAND 3 and NOR4 gates. Implementing this decoder without ...
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can someone explain the working /operation of FinFET?
Any resources that give in depth analysis of FinFET working would be helpful.
I read a couple of papers on IEEE but most of them had very little information related to the working principle.
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Miniaturization of MOSFET vs. Resistors
I've been studying some vlsi lately and came across instances where the author mentioned that it is easier to use MOSFETs at the micron level than it is to use a resistor. Therefore at many instances(...
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Transistors sizing on commercial VLSI custom design projects
I have a doubt regarding the way circuits sizing is carried out in custom design style commercial projects.
For example, let consider the design of a fast adder for a high performance CPU.
At logical ...
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Doubt regarding static timing analysis - setup time check
I was reading J.Bhasker's STATIC TIMING ANALYSIS book. In that book, he tells that when launch flip flop launches the data & while capture flip flop is capturing data, he says that
We now ...
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Selecting Time period with multiplexer
Varying input signal I want to select delay line based on the time period of input and tap out the output of delay line to input to Multiplexer.
For Example: Input Time period 1ns the input to Mux ...
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Why simulation of single NMOS/PMOS on LTspice has big difference with manual calculation using Level 1 Standard Parameters?
I am researching the mode of operation on PMOS and NMOS using Level 1 standard parameters.
This is the information of the NMOS circuit to be designed.
Using transistor model level 1 parameters, ...
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