I have a doubt regarding the way circuits sizing is carried out in custom design style commercial projects.
For example, let consider the design of a fast adder for a high performance CPU. At logical level I would opt for a Kogge-Stone or Brent-Kung adder.
But what about transistors sizing in order to improve performance at circuit level? I read about logical effort method on VLSI books. I understood this approach has limitations, and it doesn't provide closed form solution for complex netlists for which only numerical solutions are available using minimization tools.
My question: how does transistors sizing is carried out on commercial projects? Are there tools that perform the transistors sizing using numerical algorithms or this task is carried out by hand in some way?
In the first case, can someone provide some examples of a commercial tools used for the task?
