Skip to main content

Questions tagged [chip-design]

Anything related to the design of integrated circuits (chips).

-1 votes
0 answers
39 views

What kind of PLL is typically used for the digital logic in high-frequency ASIC's? [closed]

Want to generate clocks up-to 2GHz from the PLL internal to the ASIC for the critical data-path logic, please advise. Thanks! Looks like there are wide variety of PLL's, dithered, multiphase, Fs, etc. ...
necro's user avatar
  • 27
23 votes
8 answers
6k views

How do computers prevent computational errors?

Say one transistor fails and causes the entire computation to be wrong, how does a computer check to see if it is correct? My only guess is that it does it multiple times across different units. I ...
Waterbloo's user avatar
  • 349
0 votes
1 answer
68 views

What is the need for implementing synthesizable linked list module in RTL?

Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs. Given that synthesized hardware has static memory size, what's the ...
HWDesigner's user avatar
15 votes
1 answer
2k views

What is the standard procedure for analogue IC tapeout?

This is probably a very broad question and I will try to be more specific. I'm asking this question to get a sense of the gap between my knowledge and a 'successful' tapeout, as I've heard many people ...
Jack Black's user avatar
0 votes
2 answers
98 views

"Click-to-reset and hold-to-bootloader" button design scheme for an ESP32-S3 development board design

I'm trying to design a development board using an ESP32-S3 MCU. The goal is to have the boot select button act as the lone button as well as do this with a completely analog design: When the ...
Gigoiy's user avatar
  • 1
5 votes
4 answers
527 views

When to have a pathway to ground in op-amp/comparator input?

When having a comparator IC, when should I put a resistor in series, to ground, or neither? I have three examples below: I understand ex1 may be useful to reduce offset voltage due to offset current. ...
ludicrous's user avatar
  • 1,163
0 votes
2 answers
53 views

Disconnecting load circuit from reference [current mirrors]

I have started learning microelectronics design and I am currently working on my bachelor thesis. There's one thing I wanted to ask you about current mirrors and its switching. My thesis is mainly ...
tom_ger's user avatar
  • 63
1 vote
2 answers
201 views

Ethernet MAC Controller IC design process

I'm from an embedded software background, and I am trying to learn more about chip design. To this end I want to understand what goes into designing and implementing a digital IC like an ethernet ...
NeedToKnow's user avatar
2 votes
1 answer
228 views

What are the difficulties in making e-beam lithography common? [closed]

3D printers are common and cheap. An e-beam lithographer doesn't seem much more difficult; laying down the photoresist seems pretty similar, and drawing lines with an e-beam doesn't seem very hard. ...
programjames's user avatar
0 votes
1 answer
51 views

Capacitances for inverter delay calculations

In CMOS VLSI DESIGN, Neil WESTE, page 144. "The source-to-body capacitors Csbn1 and Csbp1 have both terminals tied to constant voltages and thus do not contribute to the switching capacitance. It ...
South goodman's user avatar
7 votes
2 answers
2k views

What's the point of memory compilers like OpenRAM or Synopsys Memory Compiler?

I am relatively new to ASIC design. I have experience at RTL design level and have successfully developed designs on FPGA's, but the ASIC world is still new to me. I don't have access to commercial ...
Nadax's user avatar
  • 73
1 vote
3 answers
247 views

Why is the Vcc pin almost always next to the GND pin?

I have went through numerous times where the Vcc pin is shorted with the GND pin causing damage to the entire microcontroller, for example, pins 3 and 4 and pins 5 and 6 in the ATmega328P : Image ...
John Sall's user avatar
  • 251
2 votes
1 answer
153 views

How does Vds affect the overall transconductance of this OTA?

I am trying to determine the sizing of transistors in the OTA as shown below, using the gm/id methodology. I wanted gm1 and gm2 to have much larger gm than the other transistors to reduce noise. I ...
Jack Black's user avatar
4 votes
1 answer
265 views

What are the possible implementations of LUT on silicon?

I'm looking for the possible ways to implement a LUT. The only way I know is to use Flip Flops to store the outputs and a MUX to select the output using the input as a select signal. Is there any ...
Hmdee's user avatar
  • 51
0 votes
4 answers
969 views

What is the reason some microcontrollers are designed to be powered with 5V or 3.3V while the most common battery is 3.7V? [duplicate]

As we know, most batteries' voltage is rated 1.5V (alkaline) and 3.7V (Li-Ion). Indeed, alkaline battery will be 1.65V when it is new, while Li-Ion can reach 4.2V when it is fully charged. Most ...
AirCraft Lover's user avatar

15 30 50 per page
1
2 3 4 5
7