All Questions
12
questions
1
vote
1
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330
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Multi-input NAND gate or Multiple 2-input NAND gates (VLSI design)
I am unsure which option is best practice from those featured in the title. This is part of some VLSI coursework I am doing in Cadence and so will need to do the layout of this design as well.
For ...
- 13
0
votes
1
answer
351
views
CADENCE wireless connection
I would like to know if you have a way to call without needing a line of communication at CADENCE?
See the example in the PROTEUS software image, at the time I made the connections without needing ...
- 371
0
votes
1
answer
169
views
Logic Synthesizer generates bad timings
I have a verilog code that describes a simple RAM. I use Genus synthesis tool to do synthesis, then generate a .sdf file for post-synth simulation. However, The tool generates .sdf file with faulty ...
- 143
0
votes
2
answers
178
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What tool produces this type of layout?
I don't under this layout figure (5.c) in pic attached.
This is a screenshot from research paper in this link:-
https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7573442
Alternate link for the ...
- 484
2
votes
2
answers
876
views
Parasitic insensitive switched capacitor circuit
I'm trying to simulate the parasitic insensitive switched capacitor circuit shown here:
I am using cadence virtuoso. My input is a sine wave of 1 V amplitude, 0 DC and 1 kHz frequency. I am using ...
3
votes
0
answers
194
views
Reducing the offset voltage of a source follower
I am currently trying to reduce the offset voltage of the circuit attached below to less than +/- 2mV over a 1V to 4V input range.
I have a few constraints for this task:
I can use ...
0
votes
1
answer
2k
views
Switching threshold of CMOS inverter [closed]
How to find the switching threshold of CMOS inverter from it's transfer characteristics in Cadence Virtuoso?
- 43
0
votes
1
answer
5k
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D flip-flop in Cadence
I am designing a D flip-flop. While doing my pre-layout simulations, I wasn't getting the output Q for the inputs, see attachments.
But when I tried to take the output from CLKPULSE, I was getting ...
1
vote
1
answer
1k
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Why use more than one contact in VLSI layout?
I saw the following layout in one of the standard cell library provided to us by the University. In the layout, the yellow color diffusion layer is connected to blue color horizontal M1 metal layer ...
- 793
-1
votes
1
answer
302
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Simulating Voltage regulator LM7805 in Cadence Virtuoso
I want to simulate the voltage regulator 7805 in Cadence Virtuoso and for doing so I've downloaded the data sheet for the schematic diagram. As I've intentions to strictly use pmos and nmos from the ...
1
vote
1
answer
2k
views
NAND gate LVS problems in Cadence Virtuoso
I don't know why my layout won't pass LVS. I am constructing a NAND gate, and it looks like I have all connections in the schematic and layout fine, but I can't get it to say success. What could be ...
- 201
1
vote
1
answer
5k
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How to create variable clock frequency source in Cadence Virtuoso?
I am working on Delay Locked loop Project. I want to check the lock range of the dll. I am using vpulse for clock but by giving parameters clock period, clock width, rising time, falling time. It ...
- 21