Questions tagged [asynchronous]
The asynchronous tag has no usage guidance.
19
questions
-2
votes
1
answer
122
views
3 bit Asynchronous Counter
> Blockquote
In our lab, using digital trainer kit, we designed the 3 bit asynchronous counter using JK flip flops by connecting clock to pin 1, following this circuit:
We had three inputs that ...
- 21
-1
votes
1
answer
60
views
Self clock synchronization in NRZ-I encoding
I was going through NRZ-I encoding technique, somebody mentioned that long stream of 0's will cause loss of synchronization in NRZ-I encoding scheme. But how?
What I understand is the receiver should ...
- 1
0
votes
1
answer
33
views
How to interpret timing of cascading async SRAMs
I am reading the datasheet for a 32k × 8 asynchronous SRAM (part IS61LV256AL) and wondering how to apply the timing diagram to the following circuit:
We have three identical SRAM parts with inputs ...
- 295
0
votes
2
answers
156
views
How does the second flip-flop in a naive synchronizer "prevent a metastable state from propagating"?
In this very nice answer it's explained that, fundamentally, a two flip-flop synchronizer's basic operation is to prevent the propagation of a metastable state (effectively, an invalid logic level) ...
- 1,161
2
votes
1
answer
394
views
The logic gate design of a positive edge triggered, master slave d flip flop with asynchronous inputs preset and clear?
I'm a computer science student who's trying to get a better understanding of the d flip-flop. My project assignment is to make a CMOS design of a positive edged d flip-flop using ff master slave and ...
0
votes
0
answers
50
views
Can a buck converter functioning in CCM have non-linear behaviour at light load currents?
I've been designing a Simulink/Simscape model of a TI buck converter launchpad (https://www.ti.com/tool/BOOSTXL-BUCKCONV) and I'm trying to have my model fit the behavior of the device.
The board can ...
- 1
-1
votes
1
answer
368
views
D Flip Flop Design on Logisim
I am trying to build a D flip-flop but I can´t get rid of those red wires. Is there a way to solve this?
EDIT: I was able to fix it manually through step-by-step simulation, but I still would like to ...
0
votes
2
answers
155
views
Interfacing TLC59731 with Attiny85
Has anyone had any experience communicating with a TLC59731 from an Attiny85? I'm not sure how to configure the USI to support the EasySet "protocol" described in the datasheet. I imagine I ...
- 743
1
vote
1
answer
944
views
Verification of asynchronous FIFO
I am completely new to the SystemVerilog world, and I am trying to verify the asynchronous FIFO made by Cummings.
The goal is to verify this design by using the Tb components, so no UVM at all. I ...
1
vote
1
answer
96
views
Asynchronous FIFO: Should I focus only on the top_level or maybe focus on the modules within the top_level design?
For the first time, I am approaching the world of Verification by using SystemVerilog, and I have learnt about the TB components only recently (Generator, Driver, Monitor etc.). My actual task right ...
2
votes
1
answer
61
views
Can I use a 3-phase driver like FNB41560 on 1- and 2-phase motors too?
I want to reduce complexity on buying many different parts and design different circuits. So I'm thinking if I can buy just FNB41560s that are well priced and simple and are capable of driving 3-phase ...
- 69
2
votes
1
answer
758
views
Timing Async Reset with Sync Deassert
I've been reading about FPGA resets, particularly the links in benefits of removing reset in an FPGA design and the article http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf. For my ...
- 21
-2
votes
1
answer
639
views
STA timing closure for asynchronous FIFO
I have implemented an asynchronous FIFO
However, I have setup timing violation when read_clk is having phase shift of 270 degrees , and write_clk is having phase shift of 90 degrees.
Both read_clk and ...
- 535
0
votes
4
answers
908
views
How are "async/sync" and "serial/parallel" communications related?
I think "async/sync" and "serial/parallel" are orthogonal concepts. There can be 4 combinations of communication types:
async serial
sync serial
async parallel
sync parallel
From ...
- 1,192
-10
votes
3
answers
635
views
Does this combinational lock circuit contain any memory?
Consider a simple lock circuit built using a 4-bit, active HIGH digital comparator. The first input is variable; it is the input that unlocks the lock. All the bits of the second input are tied to ...
- 2,331