All Questions
Tagged with vlsi timing-analysis
19
questions
0
votes
3
answers
146
views
Pin inductance vs pin capacitance in determining rise and fall times
I am a beginner in digital electronics and VLSI.
I know that pin capacitance is an important parameter in determining the rise and fall times of logic gates and ICs.
This is supported by my intuition ...
0
votes
1
answer
733
views
Pin vs Port terminology in SDC
In SDC (Synopsys Design Constraints), set_driving_cell is said to be used to model the drive resistance of the cell driving the input port. I'm confused by the word ...
- 1,074
0
votes
1
answer
335
views
CPU Dynamic voltage frequency scaling - does reducing both frequency and voltage always imply reduction in current?
Referring to the equation for dynamic power P=C·V2·f, is it always assumed that reducing voltage and frequency means a reduction in power and therefore current?
Example: let's assume for this argument ...
- 11
3
votes
1
answer
2k
views
How to correctly constrain a clock network with lots of mux branches?
Let me simplify a common clock network structure used in my company:
Firstly, there're multiple true clock sources (PLLs, external input, or RC OSCs).
Right at the beginning when these sources are &...
- 351
4
votes
3
answers
3k
views
Propagation and contamination delays with different delays for rising and falling edges
In the Digital Design and Computer Architecture by David Harris, Sarah Harris the authors explain what are propagation delay and contamination delay in the following way:
The propagation delay \$t_{...
- 143
0
votes
1
answer
2k
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Why Tcd and Tpd is different in combinational ckt?
In book Harris & Harris , there is a statement that Contamination delay \$T_{cd}\$, and Propagation delay \$T_{pd}\$ are different due to following reasons:
Different rising and falling delays,
...
0
votes
1
answer
2k
views
Calculating propagation delay for a logic circuit
Given the above combinational logic diagram, How to calculate the propagation delay?
AND->OR->AND-NOT
NOT->AND->NOT
I see the above two longest paths. So what I understand is just take ...
- 3
2
votes
1
answer
565
views
Application of set_clock_latency
I am learning about VLSI static timing analysis (STA) and some applications of SDC commands. I'm probably still missing some big picture concepts, but my question is about "why" when it comes to using ...
- 705
0
votes
1
answer
277
views
Doubt regarding static timing analysis - setup time check
I was reading J.Bhasker's STATIC TIMING ANALYSIS book. In that book, he tells that when launch flip flop launches the data & while capture flip flop is capturing data, he says that
We now ...
0
votes
1
answer
81
views
Expected output of DFF_2 if DFF_1 has hold violation
I am trying to figure out the output of flop DFF_2 when
If DFF_1 has hold violation.
My answer - DFF_2(Q) = X
If DFF_2 has hold violation.
My answer - DFF_2(Q) = X
I understand the FF's go to meta-...
- 3
1
vote
3
answers
134
views
Use condition from one clock with registers from another, synchronized clock
Is it permissible to use a condition generated by one clock with another, fully-synchronized clock (generated by a PLL with 0 phase shift) of different frequency?
This works as expected in simulation:...
- 1,063
0
votes
1
answer
235
views
Why only shared resistances are taken into consideration while computing Elmore delay?
While we compute the delay , using Elmore delay model we take into consideration the shared resistance and capacitance. I would like to know why are we only concerned with shared resistance not the ...
- 11
2
votes
2
answers
855
views
How do you determine if a chip has either hold or setup violation after it has been manufactured?
Suppose a chip was taped out without proper timing analysis. After you get the chip back, what kind of testing is done to check if there are any setup or hold violations in the chip?
- 135
1
vote
2
answers
1k
views
Edge aligned Source synchronous outputs
This is a basic block diagram of source synchronous interface I found in altera document.
Here
This is how edge aligned source synchronous output looks like.
They say the reciever will shift the ...
- 2,772
3
votes
1
answer
2k
views
Use of clock in SDC style IO constraints for FPGAs
Question on use of clock in SDC style IO delay constraints
The intention of this write up is to cast some clarity on how an FPGA IO interface has to be constrained. As a preamble the two timing ...
- 53