Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
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Memory view is showing multiple bytes change after a single byte is assigned to a register. Why?
I am debugging an issue I have on a legacy codebase that is running on an atxmega32c4u chip. I am writing single bytes to registers in PORTC, but the memory view is showing multiple bytes change. The ...
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Is it possible to adapt a laptop sata connector with flex? [closed]
Good morning everyone,
I need your expertise to solve a problem I'm facing. I have a laptop with a missing data and power flex cable for the hard drive, which connects to the motherboard. All the ...
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SRAM not writing properly after radiation exposure
I have an SRAM memory device GM76C88AL with this datasheet. The RAM was exposed to a radioactive beta source (~2MeV) for some time (about 2 hours). The source was just right above it (placed on it), ...
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Creating ping-pong buffer using a simple dual port RAM
In this buffer, we have two sections. Let's call these A and B. At one time we write into one but read from the other. So we write into A and read from B, or we write into B and read from A. We can ...
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How to access more storage?
I am doing a project with an STM32 chip. It needs to access megabytes of storage, but the chip can only access up to 32 Kilobytes of Flash memory.
Is there a way to add more memory?
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Simplest way to interface a high-speed (125 Msps) ADC: FIFO, RAM, SerDes or FPGA
I have a 1.8 V, 125 Msps ADC (ADS4125) with an output of 12-bit parallel LVDS or CMOS. The system is operating in bursts: the data is sampled for 8 - 30 us, with a 100 ms wait time in between. I need ...
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How to handle unused 32-bit data, dqs and dbi on DDR4 SODIMM module
In a design, I have used a DDR4 SODIMM module, which has 64-bit data, thus 8 groups of data (DQ), DQS and DBI.
However, I will only use the lower 32 bit on the module, thus have to handle the ...
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How are oscilloscopes able to fill DDR SDRAM memory without interruptions from memory refresh?
From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand ...
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Weird SRAM failures when heat is applied to the system and when probed
I'm providing assistance on a project that is encountering some interesting behavior on an SRAM memory device when environmental temperature goes up or when someone probes/touches lines associated ...
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Behaviour of uninitialised RAM in an ASIC
This is a question for anyone with experience designing or with a deep knowledge of volatile memory in an ASIC. E.g. chip designers or silicon process engineers.
We are using the ET1200 EtherCAT ASIC (...
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STM32H matrix-vector-multiply throughput
Ill be working with a board that has a STM32H743 on it, and I have a hard time reasoning about the f32 matrix-vector multiply performance I can expect of the m7 core. As I understand the core itself, ...
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What does transfer rate in RAM actually mean? How do you actually measure it?
From what I gather, transfer rate is how many bits you transfer via the bus at once with every clock. So the formula would be: frequency (in MHz) * 2 (because of DDR) * bus width (because I think it's ...
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Memory clock and Bus clock
The bus clock rate is how many times per second data is transferred from one component to another. If we consider DRAM DDR4-3200, the clock frequency of the RAM bus today can be 1600 MHz at the same ...
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What is the need for implementing synthesizable linked list module in RTL?
Curious to understand the use case of designing synthesizable linked list in RTL. This seems to be common in network chip designs.
Given that synthesized hardware has static memory size, what's the ...
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What is the DDR4/5 Colum-to-Column access latency for within bank access
Since DDR4, the banks are divided into bank-groups, where Column-to-Column delay (CCD) for accessing in different bank-groups is lower (tCCD_s) than than of accessing bank-to-bank within a bank-group (...
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