All Questions
43
questions
1
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1
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89
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How are oscilloscopes able to fill DDR SDRAM memory without interruptions from memory refresh?
From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand ...
- 23
0
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0
answers
27
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What is the DDR4/5 Colum-to-Column access latency for within bank access
Since DDR4, the banks are divided into bank-groups, where Column-to-Column delay (CCD) for accessing in different bank-groups is lower (tCCD_s) than than of accessing bank-to-bank within a bank-group (...
- 324
0
votes
0
answers
69
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SDRAM and I2S on STM32
I am using an STM32F429 discovery board to develop a DSP platform for making some sound effects. I have I2S streaming and passing through, and I have SDRAM configured where I can talk to it and even ...
- 95
1
vote
1
answer
140
views
How does DDR SDRAM increase the bandwidth without increasing the frequency at which a memory array operates?
I am reading about SDRAM, and how the bandwidth was increased with DDR optimizations. From my understanding DDR can send data at a rising and falling edge, effectively doubling the data being sent. ...
- 11
3
votes
0
answers
47
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How to verify if SDRAM alternative is a direct drop in replacement?
I'm trying to verify whether the two SDRAM chips are complete drop in replacements of each other. I've verified the footprint, electrical characteristics and various timing parameters (namely CL, tRCD,...
- 51
3
votes
1
answer
680
views
In DRAM, why does the precharge operation come after the activate operation and not vice-versa?
Precharging sets the bit line voltage is set to Vdd/2. To read from a dynamic memory cell, the bit line voltage must be near Vdd/2 for the sense amplifier to amplify the data value correctly. Since ...
- 203
5
votes
1
answer
1k
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Is my understanding of DRAM memory array topology in relation to "rows" and "columns" correct?
Assume a x16 DDR SDRAM module with 2b banks, which are made of 2r rows, which are further composed of 2c columns, where each column is 2w bits "tall". Assume that the interface is burst-...
- 203
1
vote
1
answer
198
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DDR4/DDR3 CK and CK# speed ans CLK speek
I am reading the DDR4 specification from Micron but cannot get around one thing:
When you buy RAM and it says DDR4-3200MHz, does it refer to the speed of CK and CK# pins?
I think this is not referring ...
- 171
0
votes
0
answers
80
views
For SDRAM, how to tell how many ranks supported in each channel?
This is from Wiki:
As an example, take an i945 memory controller with
four Kingston KHX6400D2/1G memory modules, where each module has a
capacity of 1 GiB. Kingston describes each module as composed ...
- 41
0
votes
1
answer
180
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SDRAM full page burst mode stoping
I'm working on an SDRAM controller to handle a frame buffer. I want to know, Is it possible to terminate a full-page burst mode by a PRECHARGE command? Although a <...
- 121
1
vote
2
answers
129
views
Do bank/rows/columns based NOR flash memory exist?
SDRAM supports more addresses than their address bus width allows thanks to the bank/row/column scheme it's based on.
My question is if there are non volatile parallel memories that are based on the ...
- 269
0
votes
2
answers
159
views
ddr3 content after intialization
I am verifying a memory interface to MIG IP from Xilinx.
The MIG IP is connected to a ddr3 SDRAM from Micron. I have a ddr3 model from Micron that I included in my testbench.
I waited until the ...
5
votes
1
answer
4k
views
why pre-post amble is required?
why do we need pre-post amble for READ or WRITE DQS ?
1 ) one reason could be -->
Because transitions of voltages from logic level 0 to 1 or 1 to 0 take time to complete: so the strobe is asserted a ...
- 61
3
votes
2
answers
12k
views
STM32H7 with 512MB SDRAM
I'm considering to design an audio processor based on the STM32H7. I want to experiment with MCU-based DSP instead of using a dedicated DSP. I chose this high-end ARM MCU to have ample headroom for ...
- 439
1
vote
1
answer
640
views
DRAM memory organisation
I've been trying to understand the working of DRAM chips but apparently in a lot of confusion.
Suppose there are 8 banks in a single chip on a module. Is it only one bit that comes out of a single ...
- 21