All Questions
Tagged with memory digital-logic
61
questions
1
vote
0
answers
59
views
Creating ping-pong buffer using a simple dual port RAM
In this buffer, we have two sections. Let's call these A and B. At one time we write into one but read from the other. So we write into A and read from B, or we write into B and read from A. We can ...
- 12k
0
votes
2
answers
95
views
Is the communication between memory controller and RAM serial?
I used to think that the communication between memory controller and RAM is parallel since we know that a RAM stick has multiple pins, just like this:
But then, from Wikipedia article on memory ...
- 443
1
vote
2
answers
87
views
Problem in executing the memory stage that can perform call, ret, pop, etc
I am trying to implement a Y86 processor for my college assignment.
This is my MemoryStage:
...
1
vote
2
answers
55
views
How is the structure of a matrix addressable memory block realized?
Currently studying memory addressing in IC design, my professor mentioned matrix addressing and how it reduces the number of input lines to the memory block. But he didn't make himself clear on the ...
- 13
1
vote
2
answers
184
views
Why do AVR microprocessors have two ways (paths) to access I/O ports?
I've an ATmega328P.
Register Summary Page 275 ATmega328P datasheet.
The first address is the I/O address, and the second is the data memory address.
I'm going to set all (D ports) Data Direction ...
- 27
1
vote
1
answer
186
views
Using SRAM Macro for simulation and synthesis
I got my hands on this ARM Artisan memory compiler for generating SRAMs. I generated .v and .lib files from it to carry out RTL ...
- 319
0
votes
0
answers
61
views
Type of memory used to design Arbitrary Waveform Generators (AWGs)
i am interested in understanding how the design decision is taken while choosing the type of memory to be used in AWGs. My understanding is that in most AWGs, waveforms are stored in a Digital memory ...
- 402
1
vote
1
answer
136
views
Bitline is not working correctly (6t cell sram with sense amp and precharge)
After simulating 6t ram with sense amplifier and precharge, bit line value is fixed to 1.5v. How can i avoid this? Using pspice to simulate.
0
votes
1
answer
156
views
Asynchronous read memory causing hold violations in an FPGA
I have a pipelined CPU design in Verilog that uses a memory block whose reads are asynchronous. I have usually had separated memory for instructions and data and everything worked fine, but recently I ...
- 1,259
1
vote
4
answers
1k
views
How are ones and zeroes stored in a computer physically?
As I mentioned in the title "physically", when the computer is off and there is no power, how are the bits stored? For example, how can an image be stored?
- 89
1
vote
0
answers
26
views
DDR interfacing with rockers3399 processor
I am using rockers 3399 processor in one of my applications. if you see page no 9 'External Memory or Storage device' section you can see the below things
*Support 2 channels, each channel is 16 or ...
- 2,593
0
votes
2
answers
362
views
Saving a bit state with OR Gate using transistor doesn't work
I want make simple 1-bit memory using OR Gate like this picture
It's working what I expect when using OR gate component. I change first input state to 1 so that it will give an output state of 1. ...
2
votes
1
answer
2k
views
The concept of DDR rank
I have an understanding of DDR rank which I think is incorrect. If someone could join the dots then there would be more clarity.
Here is what I know
A DDR rank is a 64bit interface consisting of x8 ...
- 379
0
votes
0
answers
34
views
How do I read the value of registers in Logism?
I am designing a CPU in logism. One of the components of the CPU is a register circuit (RegFile), which stores the registers data. The register circuit (RegFile) is shown below:
I am able to write ...
- 113
0
votes
0
answers
60
views
Do SRAM Macros register the inputs?
In ASIC design, we often purchase SRAM macros to use in our designs. A typical SRAM macro includes a Verilog description and a timing/layout characterization (lib file).
My question is this: SRAMs ...
- 143