All Questions
23
questions
1
vote
2
answers
87
views
Problem in executing the memory stage that can perform call, ret, pop, etc
I am trying to implement a Y86 processor for my college assignment.
This is my MemoryStage:
...
-1
votes
1
answer
56
views
Synchronising data input and filter coefficient so that both reach at same time and give filter output in semi parallel/parallel filter in Verilog
I have designed an 8-tap filter using 8 coefficients in a semi-parallel fashion. I want to get the correct output for a FIR filter design by using 8 DSPs and one SRLC32E register. Here I pass my input ...
0
votes
1
answer
156
views
Asynchronous read memory causing hold violations in an FPGA
I have a pipelined CPU design in Verilog that uses a memory block whose reads are asynchronous. I have usually had separated memory for instructions and data and everything worked fine, but recently I ...
- 1,259
0
votes
1
answer
568
views
Writing into a full FIFO
I am using a FIFO as a temporary memory block to store values and then perform some calculations between the neighboring values once the FIFO becomes full. After the calculations are finished, I would ...
- 578
1
vote
1
answer
757
views
tRAS definition for DDR memory
In Figure 3 of https://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh , why tRAS is defined as the max timing between two REFRESH commands ? This ...
- 413
0
votes
1
answer
1k
views
How to Use Addresses with Single Port RAM on FPGA
I am trying to understand this example of single port memory where an 8 by 64 bit RAM is created. If I am understanding correctly, the section of code that says "reg [7:0] ram [63:0]" means ...
- 67
1
vote
1
answer
846
views
1
vote
1
answer
211
views
Interfacing multiple SPI data input into EBI memory for access in verilog
I have several SPI peripherals that collect data into the FPGA and I have an EBI memory module to communicate data from FPGA to micro controller. I am having a hard time understanding the best way to ...
- 13
1
vote
2
answers
369
views
If I need to access memory cell by cell, should I shift or index?
I have a piece of memory which I need to access cell by cell:
parameter RAM_LENGTH = 1024;
reg [7:0] mem [RAM_LENGTH - 1:0];
I need to iterate cells sequentially....
- 858
0
votes
1
answer
2k
views
Using generate statement in Verilog
I am using nested for loops using generate module for creating multiple instances of sub-modules in verilog
this is for finding 4x4 determinant. I generated the sub-modules with inputs given ...
- 1
1
vote
1
answer
983
views
Reseting a 128 adress* 16 words memory
I'm doing my term project, in which I have a memory, which can be changed by the user. The specification is that whenever reset is activated, data on this register should be reset to all zeros.
I ...
-2
votes
1
answer
2k
views
how to determine the column address
Does a normal ram require to have row and column address decoder?
From the ram verilog coding that i get from http://www.asic-world.com/examples/verilog/ram_sp_sr_sw.html.
In the verilog coding, it ...
- 1
0
votes
1
answer
555
views
Can't Search for specific value at RAM - verilog
My module has search for specific value at RAM and then return its location address.
when I wrote a test bench, I see that the module didn't work correctly! always the output value is "don't care". ...
- 101
0
votes
1
answer
1k
views
searching in memory at verilog
I need to make a module which responsible to search overall memory to find a specific value and return the address location, but I have the following error after do Synthesize in Xilinx.
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- 101
1
vote
2
answers
7k
views
Verilog module to read/write a register
I would like to create a module that can change the value of a register passed to it (+/- 1) using an inout port. I wrote this:
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- 11