1
\$\begingroup\$

From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand that at high frequencies, thanks to burst refresh, it is possible to fill a significant part of memory without refreshing (and use burst refresh after that). But they write to SDRAM at lower sampling frequencies as well. So the refresh has to happen somewhere. How do they do that? Some clever refresh tricks? Or am I missing something?

\$\endgroup\$
1
  • 2
    \$\begingroup\$ Smaller amount of SRAM inside the MCU or FPGA or whatever manages the sampling could easily buffer the samples during the refresh period. \$\endgroup\$
    – brhans
    Commented May 26 at 22:03

1 Answer 1

1
\$\begingroup\$

The DDR RAM works in bursts anyway.

So data has to be cached or buffered into larger chunks than 1 byte to use the available bandwidth of the memory.

And as there is a lot of bandwidth available, the system is designed so that there is enough bandwidth for capturing waveform data, even after refresh cycles and other possible things, such as running the scope OS or display frame buffer from the same memory.

\$\endgroup\$
3
  • \$\begingroup\$ Hmm, I wonder if DDR clocking is independent from ADC clocking then... Initially I thought that they must have the same clock. But if they are sufficiently independent then I'm not so sure... \$\endgroup\$
    – Dmitry
    Commented May 27 at 15:18
  • \$\begingroup\$ @Dmitry Why would they must have same clocks? Even if they did, it tells nothing about how the system works, and it's useless to speculate. Just like your PC uses some memory clocks that are different from CPU interface clock or PCIe interface clock or CPU core clock or whatever clock. The memory bandwidth may not be about the clock but the width in bits. \$\endgroup\$
    – Justme
    Commented May 27 at 16:10
  • \$\begingroup\$ Well, I just used my experience with SRAM FIFO chip. In that case, I just directly filled SRAM from ADC using the same clock. Without buffers or anything. But DDR probably requires separation of tasks... \$\endgroup\$
    – Dmitry
    Commented May 27 at 16:24

Not the answer you're looking for? Browse other questions tagged or ask your own question.