All Questions
22
questions
1
vote
2
answers
69
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Memory clock and Bus clock
The bus clock rate is how many times per second data is transferred from one component to another. If we consider DRAM DDR4-3200, the clock frequency of the RAM bus today can be 1600 MHz at the same ...
- 13
0
votes
0
answers
233
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Can a PCI bus master access a device mapped in cpu memory space
If a PCI bus master can access memory space just as cpu can, can it put an address on the memory bus of the cpu that actually triggers a memory mapped I/O device to respond to that address.
(As if the ...
- 191
0
votes
1
answer
133
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How does data reach peripherals in STM32H7xx?
I'm trying to understand bus interconnection matrix in stm32h7xx. Here is a capture of the H753's one:
In particular, I'm wondering how a data buffer located in DTCM would reach the SPI1's tx ...
- 1,259
0
votes
1
answer
84
views
Externally triggered high impedance toggle for large number of parallel lines
First, I want to apologize for my terminology here -- I'm a software engineer rather than EE and I'm a bit rusty.
I have a parallel SRAM chip that is being shared by 2 CPUs that requires 19 address ...
- 131
1
vote
1
answer
310
views
Questions about MMIO
Any CPU has address pins which form it's physical address space.
Some peripherals, like ram or flash can be classified as one big data register which is mapped directly to CPU address space. On the ...
- 13
0
votes
0
answers
27
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What are odd-even memory addresses in 8086 and how do they work? [duplicate]
I have recently started to look more into microprocessors at the hardware level, and i am a bit confused on what are the odd-even memory locations that 8086 uses.
As far as i understand, it has ...
- 129
0
votes
1
answer
133
views
How do modern CPUs treat memory operations? [closed]
How does a modern CPU treat memory reads and writes on the hardware level?
With old 8-bit architectures all memory locations are read and written to one byte at a time, but how do modern CPUs that ...
- 129
-1
votes
2
answers
71
views
Data transfer from/to memory [closed]
Consider an interface (between a memory and a processor, or between a memory and an ASIC, or similar situations) in which there is a data bus of 8 bit. Suppose I want read a 16 bit data from memory, ...
- 3,550
0
votes
2
answers
292
views
Are memory-mapped registers actually implemented as real registers?
I am currently trying to better understand microcontroller-architectures and I am particularly studying the ARM cortex-m3 right now. What I have always wondered is, if memory mapped registers are ...
- 143
0
votes
1
answer
174
views
Memory chips, are the bits of a long word stored contiguously?
I am reading Structured Computer Organization, 6th edition by by Andrew S. Tanenbaum and Todd Austin. Chapter 3.3.5 talks about memory chips. I'm confused about the following paragraph, which relates ...
4
votes
2
answers
4k
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Memory interfacing with 8086
The 8086 microprocessor can address up to 1MB of memory (20 bit address bus). Most books show a diagram of this 1MB memory which in turn shows interrupt vector tables, DOS function, BIOS routines ...
- 253
1
vote
2
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716
views
Which cache type is better for bus watching?
I am studying for an exam about memory (mostly cache) and I ran across a multiple-choice question from a few years back:
...
- 163
0
votes
1
answer
68
views
A couple of questions about memory gates
Let's assume I have a memory block here, I didn't set any value to it, what value would it output?
If two outputs from two different bytes meet in the same wires, what happens? I'll give an example: ...
6
votes
2
answers
4k
views
STM32: avoiding DMA & CPU collisions
Section 13.4 of the STM32 Reference Manual (for my STM32F303RE board) states:
The DMA controller performs direct memory transfer by sharing the system bus with the
Cortex-M4 ® F core. The DMA ...
- 316
-1
votes
3
answers
366
views
Control WR and OE lines of parallel SRAM with only 2 wires while loading data with 8
This is my circuit in relevance to my question:
I apologize for the messy wiring, but I did it that way to make my PCB production substantially easier.
My problem is I only have 10 wires available ...
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