Questions tagged [sdram]
SDRAM stands for synchronous dynamic random access memory. Being synchronous it relies on a separate clock signal for moving commands and data to/from the device.
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Stabilizing ODELAY_VALUE related to IODELAY2 module in Spartan6 SLX9 FPGA Design for SDRAM Interface
I'm working on an FPGA design for the Spartan6 SLX9, which includes a memory controller for off-chip Micron SDRAM. To introduce a delay on the clock signal to the SDRAM relative to the Data/Command ...
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STM32 - LTDC + DMA2D flickering and banding
I'm currently using an STM32H753 with 16bit SDRAM (IS42S16800F) to store an RGB565 buffer, with LTDC driving an 800x480 LCD. I'm using double-buffering, flipping the buffers in the LTDC vsync ...
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How are oscilloscopes able to fill DDR SDRAM memory without interruptions from memory refresh?
From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand ...
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What is the DDR4/5 Colum-to-Column access latency for within bank access
Since DDR4, the banks are divided into bank-groups, where Column-to-Column delay (CCD) for accessing in different bank-groups is lower (tCCD_s) than than of accessing bank-to-bank within a bank-group (...
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SDRAM logic makes noise on ADC readings with FPGA
I am working on a design in which an FGPA reads the output of a 12-bit 40MHz ADC and then stores half of the data on an external SDRAM and the other half on an on-chip BRAM after some averaging.
The ...
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DDR2 SDRAM with the Lattice ECP5
I have a FPGA design that requires some memory. I'd really like to use DDR2 because of cost and speed reasons. I'd be running it at its lowest allowed frequency of 125MHz. Now the ECP5 has some IP ...
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Decoupling capacitors where VDD/VSS pins are spaced apart
On previous PCBs I've laid out, I've always been able to place decoupling capacitors easily due to VDD/VSS pairs being close together. However, I'm now working on a design that's using a chip (ISSI ...
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Implementing DDR In/Out DQ Pin for DDR3 SDRAM on Xilinx Spartan-6 FPGA
I’m currently working on a project that involves interfacing a DDR SDRAM (Micron MT41J128M16) with a Xilinx Spartan-6 FPGA. I have implemented a controller. I’m looking for guidance on how to properly ...
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Confused about STM32 FMC pins for SDRAM
Context: I am currently working on a design that is centered around the STM32H723ZGEI6. I chose to opt for 32MB of external RAM via the IS42S16160J SDRAM IC. However, I am having some trouble figuring ...
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Calculating timing constraings for interfacing with sdram
I want to set the set_input_delay and set_output_delay constraints for my design but I'm having trouble to find the values to calculate them.
My understanding so far:
To calculate the set_output_delay ...
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SDRAM and I2S on STM32
I am using an STM32F429 discovery board to develop a DSP platform for making some sound effects. I have I2S streaming and passing through, and I have SDRAM configured where I can talk to it and even ...
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FPGA and SDRAM noise impact on ADC input
I'm using an FPGA to get data from an ADC and save them on SDRAM, the SDRAM works with 100 MHz and the ADC works with a 40 MHz clock so I use a clock IPCORE to generate them from my 50 MHz oscillator ...
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SDRAM Voltage and pin planner consequences
I have this SDRAM module:
According to the docs: am I right that it's the 3,3V version?
If yes: what are the consequences of that fact using the Pin Planner?
Is it correct that I have to set the I/O ...
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Understanding "Key Timing Parameters" of SDRAM datasheet
I'm currently trying to understand SDRAMs at the example of the iS42/45S16320d and the DE10-lite board.
At the beginning of the sheet you can find a table "Key Timing Parameters" that ...
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Timing constraints vs. NOP in timing diagram of IS42S16320D SDRAM
I'm working with an FPGA that works at 50MHz and the IS42S16320D SDRAM.
The datasheet of the RAM assumes a clock of at least 100MHz.
Given the following timing diagram:
The $t_RCD$ is 18ns which ...
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