All Questions
Tagged with memory non-volatile-memory
53
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What do NRAM cells look like?
Note: I don't have any electrical engineering experience, so I'd like to apologize for my bad vocabulary about this subject.
I'm currently exploring the memory world and stumbled across NRAM which got ...
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8
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3
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What are the "redundant bytes" added to every page of this NAND flash?
I was tinkering around some NAND flash memories and found out that some of them (not sure if it's all of them) have a few "redundant bytes" that are something of a mystery. (See related ...
- 2,017
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How long can a micro SD card hold data without being powered? [closed]
I lost a micro SD card few years ego, and I'm worried that someone may find it and misuse the data stored in it.
How long can a micro SD card keeps the data without being powered, ignoring other ...
user285637
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2
answers
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Non volatile memory on simple hardware board [duplicate]
I'm designing a low frequency board with some analog signals inputs and a few discrete logic gates which drive warning LEDs. I want to save the status of the LED even if the board is powered off. No ...
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2
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123
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Best memory choice for my sensor
I'm a software developer and trodding in murky waters here so please do forgive my lack of knowledge. I've been developing a sensor with the nRF9160DK and some accelerometers. I need to continuously ...
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1
answer
315
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EEPROM memory erase bit vs word
If I have an EEPROM 1K X 16, can I erase bit by bit or just word by word (2 bytes/16 bits) in my matrix of registers ? In digital systems - TOCCI, the EEPROM is modeled by a matrix of registers, each ...
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1
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Micron MT25QL512ABB8ESF-0SIT not working after Non Volatile Configuration register setting
I'm using the STM32H7 Evaluation board. There is an on-chip QSPI DUAL NOR CHIP MT25QL512ABB8ESF-0SIT. After setting up the Non-volatile configurations Register value to 0x89D6 and power cycle, FLASH ...
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Memory row driver does not have enough driving power
I am building the row driver of a piece of RRAM. Different from traditional memory, RRAM's cells are composed of resistor-like elements. I tried using a single inverter and a back-to-back inverter ...
- 15
1
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1
answer
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Industry Standard for Memory Address Decoder Design
I am currently designing the address decoder of a piece of ReRAM that will be sent to TSMC and manufactured. I have studied in class and textbook that there are two common address decoder designs. One ...
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1
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2
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129
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Do bank/rows/columns based NOR flash memory exist?
SDRAM supports more addresses than their address bus width allows thanks to the bank/row/column scheme it's based on.
My question is if there are non volatile parallel memories that are based on the ...
- 269
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Operative Definitions of Memory in Circuits
I've been studying Memristors (non-ideal) and some related circuits depending on pinched hysteresis of the IV for use in memory. I'm still puzzled by the lack of general framework for what constitutes ...
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3
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Storing data for a really really long time [closed]
How might one store data for the far future? (100 years and up, possibly centuries)
This is entirely hypothetical but would it be possible for semiconductor based data storage to have similar ...
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13
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8
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5k
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EEPROM being both "programmable" and "read-only"
Since it is called programmable, I tend to think that it should also be named with the write option. What is the deal here?
- 2,106
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271
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Why it is required to write each byte with 0 before erase in NOR flash?
It is written in some sites that for NOR flash, each byte has to be written with 0 before erase. Why it is required to write with 0 before erasing? Erasing the sector change each byte to 1.
- 101
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1
answer
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Is writing in FeRAM memory cell destructive?
I have read that writing in Ferroelectric random access memory is not destructive. But in a WL||PL memory architecture, if I try to write a '0' in a cell and the adjacent cell holds a '1', shouldn't ...
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