All Questions
47
questions
1
vote
0
answers
87
views
6502 Extra Cycles on Page Cross
On the 6502 processor, when using the Absolute,X, Absolute,Y or (Indirect),Y addressing ...
11
votes
8
answers
5k
views
What mechanism does CPU use to know if a write to RAM was completed?
How does CPU know that a write to RAM was successful, like how does a faster CPU know that data was successfully written to a slower RAM?
You're free to mention any system architecture because I'm not ...
0
votes
0
answers
43
views
Can we service another memory request from L1 cache when an L1 miss is being serviced from L2?
Consider the case where L1 cache miss occurred and is being serviced by L2 cache which could take many cycles (may go to main memory in case of L2 cache miss). In the meantime L1 cache is idle, in ...
10
votes
2
answers
3k
views
RISC-V Zero Instruction Question
I have seen a table of opcodes for RISC-V instructions (for base I 32 bit ISA). I am working with a RISC-V core on FPGA and had BRAM for instructions set to all zeros.
Does anybody know what happens ...
15
votes
6
answers
4k
views
Why are there separated power circuits for CPU, GPU, and RAM on a motherboard?
Even though there is a power supply unit in a computer case, why are there separated power circuits for CPU, GPU, and RAM on the motherboard?
I mean, why can not the CPU, RAM and GPU just take their ...
0
votes
1
answer
1k
views
How do computer memories interact with each other (registers, cache, RAM, ROM)?
After Googling around for some time, I have managed to get a good understanding what makes these components different, but I've yet to find any clear computer architecture-focused article/thread on ...
2
votes
1
answer
147
views
Size of a memory cache
Assuming we have a virtual address issued by a model CPU that contains a total of 32 bits and 20 bits of this address are reserved for the tag + the cache comprises a total of 1024 cache lines.
Should ...
0
votes
0
answers
34
views
How do I read the value of registers in Logism?
I am designing a CPU in logism. One of the components of the CPU is a register circuit (RegFile), which stores the registers data. The register circuit (RegFile) is shown below:
I am able to write ...
-1
votes
4
answers
552
views
Why is bool type typically 1 byte long?
I was reading: https://www.quora.com/Why-is-the-bool-type-typically-8-bits-long
And the answer was:
Because it’s the smallest type that has an individual memory address
so that you can take a pointer ...
1
vote
2
answers
195
views
ALU result is 0, how to fix this?
In system-verilog I am trying to build a small ALU unit which takes a and calculates the negative value of it (-1) in a CPU.
I wrote:
...
0
votes
0
answers
27
views
What are odd-even memory addresses in 8086 and how do they work? [duplicate]
I have recently started to look more into microprocessors at the hardware level, and i am a bit confused on what are the odd-even memory locations that 8086 uses.
As far as i understand, it has ...
0
votes
1
answer
133
views
How do modern CPUs treat memory operations? [closed]
How does a modern CPU treat memory reads and writes on the hardware level?
With old 8-bit architectures all memory locations are read and written to one byte at a time, but how do modern CPUs that ...
0
votes
5
answers
2k
views
Why are bytes 8 bits? (and more)
An 8 bit value can range anything from 0 to 255 in decimal, or 00 to FF in hexadecimal. But why did they choose 8 bits for the byte, out of all of the powers of 2 they could have chosen? Even still, a ...
0
votes
2
answers
327
views
The CPU has registers, but doesn't the RAM have registers too?
At low-level, registers are the same as a bunch of flip-flops connected by the same clock, so I would think RAM is made of registers.
I've been reading, though, that registers are only in the cpu, ...
1
vote
1
answer
491
views
How x86-64 Intel CPU understands how many bytes load into a register
I have the following byte code one the left and and its byte representation on the right:
...