All Questions
104
questions
1
vote
1
answer
218
views
What does transfer rate in RAM actually mean? How do you actually measure it?
From what I gather, transfer rate is how many bits you transfer via the bus at once with every clock. So the formula would be: frequency (in MHz) * 2 (because of DDR) * bus width (because I think it's ...
- 41
0
votes
2
answers
95
views
Is the communication between memory controller and RAM serial?
I used to think that the communication between memory controller and RAM is parallel since we know that a RAM stick has multiple pins, just like this:
But then, from Wikipedia article on memory ...
- 443
9
votes
2
answers
617
views
What is the theoretical maximum capacity of 72-pin RAM modules?
I'm asking, because the information on Wikipedia is extremely lackluster, perhaps even incorrect.
This is my current understanding:
A 72-pin module has 12 address pins, 4 CAS, and 4 RAS pins. (For ...
- 1,097
0
votes
1
answer
203
views
MUX in a 4 bit by 3 bit memory
Here is a 3-bit adressable memory with an adress space of 4.
My question is why is the book calling the 3 rightmost highlighted circuits MUXes? And what type of MUXes are they? 4:1 MUX? And if it is ...
- 91
1
vote
1
answer
140
views
How does DDR SDRAM increase the bandwidth without increasing the frequency at which a memory array operates?
I am reading about SDRAM, and how the bandwidth was increased with DDR optimizations. From my understanding DDR can send data at a rising and falling edge, effectively doubling the data being sent. ...
- 11
3
votes
1
answer
238
views
How can I improve this RAM implementation in VHDL?
I'm practicing for a lab exam and I'm trying to solve one from past years. I feel like I'm doing something wrong because I don't have much experience with VHDL.
Exam question
Write the VHDL code for ...
- 33
0
votes
1
answer
106
views
How are system clock and bus clock frequencies related?
I see a frequency in RAM specs which is different than the frequency of the system clock. Having a separate clock makes sense if RAM can't run at the same frequency, but is there a constraint that its ...
- 136
3
votes
1
answer
228
views
Why did GDDR5X implement QDR?
DDR makes complete sense to me: it matches up the transition rate between the data signals and clock, so that twice the data can be sent over a bus without increasing the overall design bandwidth. The ...
- 10.8k
0
votes
2
answers
536
views
Microcontroller and Memory size allocation
Below are two custom made microcontrollers. The only difference between this is memory size.
My question:
Can someone tell me what is their start address and end address? Like, for the first one - ...
user220456
3
votes
4
answers
5k
views
What does High-Impedance mean in digital systems?
I'm currently messing with the Microchip 23LC1024 SPI RAM chip, and trying to read the datasheet to understand how to work with it. I'm not an electronics engineer or something like that, I'm a ...
- 235
2
votes
1
answer
283
views
What does the "In-line" in SIMM and DIMM memory mean?
I've been searching for what exactly the "in-line" part means but I don't get it. Is it the way the chips are positioned, as in a line? If it is, is there another possible configuration?
- 123
4
votes
4
answers
3k
views
How is a memory location accessed by random access?
This is a comment that I saw in another forum:
Like any other memory storage, it's divided into smaller units. These units can contain data individually or can be treated as a big single block of ...
- 143
0
votes
1
answer
384
views
How do you figure out the decoder inputs for a memory expansion?
How do you know what the two inputs will be for this 2-to-4 decoder? Also, what changes would be made to the circuit if the 2 data lines are not the same?
The original problem:
I drew the circuit, ...
- 15
0
votes
0
answers
133
views
How do I get the number of address lines of 12G * 64?
The example problems I'm seeing in the book gives me nice numbers where the size of the ram can easily fit into a power of 2, but this one doesn't.
The original question:
This is all I have:
I was ...
- 15
0
votes
1
answer
95
views
Unexpected behaviour of data memory in modelsim testbench
I am describing a very simple ram memory in VHDL and observing strange behaviour which I do not
understand nor am able to debug. I have similar code written elsewhere and I suspect that rewriting it ...
- 1