Questions tagged [memory]
Consider instead more specific tags, e.g., dram, sram, flash
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Core memory output line question
How is a bit read from the core memory pictured below? I understand current through 1 and 1 vs 0 and 0 will change the torus magnets field setting a bit. I’m confused how this field is read back using ...
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Bit Banding in STM32 CORTEX M4
I am confused in the bit banding of Cortex M4. I was going through the datasheet of STM32F446ZE and found in the memory map there was only written SRAM (112 kB aliased
By bit-banding) What does that ...
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How does PCIe work?
I have gotten very confused with how PCIe works. I read that PCIe is a memory mapped protocol. That is, if the GPU wants to write to the CPU it will access the DDR memory located on the motherboard ...
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Remote update firmware for MCU
I am planning to implement a remote firmware update for my MCU and seek recommendations on the necessary features for the MCU. Specifically, I would like to understand the requirements regarding ...
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DDR4 Routing Consideration
I'm designing a new PC based on Intel Tiger Lake UP3.
In Intel Design Guide, I saw that there recommendation for DDR4 signals is to have two BO segments (BO1 and BO2).
each BO has different impedance ...
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DDR3 Termination resistor value regarding
In a design, my senior put a 49.9ohm termination resistor to terminate the control, address, and control lines.Here I can't find the correct explation for this.
My question is,
1.How to choose the ...
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STM32F4 NAND flash via FSMC, difference between bytes written and read back
I have a Waveshare Open407V-D development board, basically a "motherboard" in which an STM32F4DISCOVERY kit is fitted (this kit, for those not familiar with it, is made by ST itself and based on the ...
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How memory is stored in memories like SD Card, USB flash drive, etc. that the data stays even if removed to the device?
This latches ( Gated Latch, SR Latch, and Flip Flops) can only store memory IF there is electric current flowing, but everything will go OFF if no current.
I wonder how memory is stored in memories ...
CommunityBot
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Memory view is showing multiple bytes change after a single byte is assigned to a register. Why?
I am debugging an issue I have on a legacy codebase that is running on an atxmega32c4u chip. I am writing single bytes to registers in PORTC, but the memory view is showing multiple bytes change. The ...
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Why we used 128 bytes internal RAM memory instead of 256 bytes in 8051?
... since using 7-bit in 8-bit address bus wastes one wire.
In 8051 there is a 8-bit address bus for internal RAM out of which we just use 7 wires making it addressable to just 128 byte locations, why ...
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SRAM not writing properly after radiation exposure
I have an SRAM memory device GM76C88AL with this datasheet. The RAM was exposed to a radioactive beta source (~2MeV) for some time (about 2 hours). The source was just right above it (placed on it), ...
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Creating ping-pong buffer using a simple dual port RAM
In this buffer, we have two sections. Let's call these A and B. At one time we write into one but read from the other. So we write into A and read from B, or we write into B and read from A. We can ...
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Clarification about Memory Address
I've been working with a project regarding an SRAM Controller in Verilog. As you can see, my controller should include those blocks. I've written some Verilog Code and right now I'm trying to test it, ...
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Behaviour of uninitialised RAM in an ASIC
This is a question for anyone with experience designing or with a deep knowledge of volatile memory in an ASIC. E.g. chip designers or silicon process engineers.
We are using the ET1200 EtherCAT ASIC (...
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How to handle unused 32-bit data, dqs and dbi on DDR4 SODIMM module
In a design, I have used a DDR4 SODIMM module, which has 64-bit data, thus 8 groups of data (DQ), DQS and DBI.
However, I will only use the lower 32 bit on the module, thus have to handle the ...
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