Skip to main content

All Questions

Tagged with
9 votes
2 answers
617 views

What is the theoretical maximum capacity of 72-pin RAM modules?

I'm asking, because the information on Wikipedia is extremely lackluster, perhaps even incorrect. This is my current understanding: A 72-pin module has 12 address pins, 4 CAS, and 4 RAS pins. (For ...
polemon's user avatar
  • 1,097
3 votes
1 answer
82 views

Memory Capacity and Memory Addresses

According to this site, in Table2, HBM(HBM2e) has a capacity of 8Gb = 2^33 bits per channel. Here, it has a 24-bit address consisting of 4 bits from the Bank address BA[3:0], 15 bits from the Row ...
cashew_nuts's user avatar
0 votes
1 answer
90 views

How to debug modbus rtu address space problems? [closed]

I have an "Ewon Flexy server" and an "IMO SD1 Inverter" connected via Modbus RTU RS485. I can change some of the parameters with Flexy interface and observe the change in the ...
Juha's user avatar
  • 188
0 votes
0 answers
107 views

What is the difference between Content Memory Addressing (CMA) and Content Addressable Memory (CAM)?

I have been looking over the internet for Content Memory Addressing(CMA) but whenever I search for it I get Content Addressable Memory (CAM). So I am confused, is CMA and CAM the same thing. If ...
Shashi Kumar's user avatar
0 votes
1 answer
257 views

Specifying the address range of each memory block

Four 16x4bit blocks are interconnected to form a 64-bit memory as shown below First of all why is a block here called 16x4bit ; 4 bits are related to the input gates but what's with 16 here ? I also ...
Samir's user avatar
  • 227
0 votes
1 answer
193 views

Can a memory chip have a certain starting address

In my book there is a question stated: Can a memory chip of capacity 512 KB have the starting address 2B0000h? To me this seems like an incomplete question with a wrong answer in the book. The ...
user1949350's user avatar
0 votes
2 answers
1k views

Memory-mapped IO vs Port-mapped IO in microcontrollers

I've been reading about external peripheral mapping to microcontrollers. I understand that memory-mapped IO means that the same address space in the microcontroller can be used for internal memory ...
Engineer999's user avatar
0 votes
1 answer
293 views

Address decoding different bank sizes in 64K memory

I'm doing a small Motorola 6809-based computer project, and since I'm a bit rusty when it comes to boolean algebra I'm wondering if I'm doing my address decoding a bit too complicated for my simple ...
tobier's user avatar
  • 197
1 vote
2 answers
809 views

Does pin A15 on a Z80 tell if the CPU is addressing ROM or RAM?

I am designing a simple, hobbyist single board computer similar to an Arduino using a Z80 CPU. The trouble I am running into is how the CPU addresses memory. I know that the Z80 uses pins A0-A15 to ...
Shades's user avatar
  • 113
-5 votes
1 answer
699 views

Design logic circuit to address 2 x 512 kB RAM and 2x1024 MB RAM with 36 address lines? [closed]

How do you address 2 x 512 kB RAM and 2 x 1024 MB RAM with 40 address lines? Memory is byte addressable, problem is to find out enough address lines to address all 4RAM and designing appropriate ...
Ajakma's user avatar
  • 91
1 vote
1 answer
117 views

Relate Bin file (read from uC) to map file

We have a AT32UC3C1512 presenting a Failure, part of the analysis that is normally performed to isolate the failure is to perform ABA swap of components, we have performed the swap in several ...
user2982010's user avatar
3 votes
2 answers
4k views

Arm mode and Thumb mode makes the PC's bit 0

The ARM and Thumb modes are word-aligned and halfword-aligned. I understand this means that if it's in ARM mode, the start of addresses must be divisible by 32, and if it's in Thumb mode it has to be ...
stumped's user avatar
  • 145
0 votes
1 answer
88 views

Choose "safe" section of DDR memory in ZC702 board

I can not fully understand what section of the available external memory is safe to assign for a VDMA on the ZC702 board. I need to dedicate 4MB of memory for the three frames (640*480* 4bytes * 3 ...
Nazar's user avatar
  • 3,192
0 votes
2 answers
771 views

Is this address decoding circuit correct?

The problem is to design an address decoding circuit for two 4Kx8 RAM chips at the 2050H . We have 16 address lines. So, for 4Kx8 RAM we need 12 address lines to address the memory. Remaining can be ...
Happyfeet's user avatar
-1 votes
1 answer
374 views

A computer system has RAM of 32K bytes and 64 peripherals. What is the number of distinct addresses required? [closed]

Is it correct to assume that the number of addresses for 32k of ram is 2^15 addresses? Then for the peripherals is it 2^6 addresses?
MrWiseguy818's user avatar

15 30 50 per page