0
\$\begingroup\$

I'm providing assistance on a project that is encountering some interesting behavior on an SRAM memory device when environmental temperature goes up or when someone probes/touches lines associated with the data lines (if touching, ESD safety is being followed). Our setup is a custom board that utilizes the STM32F429BIT uC along with the IS61WV102416DBLL-10BLI SRAM and MT28EW128ABA NOR Flash. We have the SRAM and NOR Flash ADDR and DATA lines tied to the same FMC bank. For routing, we made sure that flyback routing was followed, length matching was met, and single ended controlled impedance of 50 Ohms was followed for all DATA/ADDR/CTRL lines. Signal integrity was done on Hyperlynx. Signal integrity pointed out a couple of crosstalk violations from some ADDR lines, so the layout was updated to fix these problems and were re-simulated to assure it was addressed.

I would like to point out that on a previous revision, no length matching, controlled impedance, and signal integrity was taken into account in regards to the routing of the SRAM/NOR Flash. Random failures would occur involving the SRAM and NOR Flash at power up/programming/in the field. It was discovering this that I recommended the team to proceed with the re-spin of the board to address potential layout mishaps that could be causing numerous issues.

Upon receiving our new boards back, SW tested the boards by running a read, write, clear test on the SRAM. At room temperature, the SRAM was running fine and did not report any errors throughout the test. We increased the surrounding temperature by carefully using a heat gun at low heat from a distance. We noticed that once the board temperature reach 85 F, the SRAM would start to show failures.

I'm a little perplexed that a small increase in temperature would lead to issues like this. I plan on making sure we are meeting timing requirements with our write and erase process, however, it's perplexing that some heat could potentially cause bit errors.

Does anyone have any experience where their memory devices on their custom board performed simple bit error tests at room temperature and then failed at slightly higher temperatures? Curious to get your insights as to what might have happened and what was done to resolve the issue.

I can provide detail schematics/drawings when I go back into the office tomorrow.

\$\endgroup\$
8
  • 1
    \$\begingroup\$ Meeting timing specifications (with account for amplitudes and shifts in receiver thresholds) over full temperature range (and over spectrum of devices from approved vendor list) per plan of record and approved specifications is pretty much the day-to-day job of professional designers and production and validation engineers. Ensuring healthy margins is a key. Apparently your interface design has little to no margins. \$\endgroup\$
    – Ale..chenski
    Commented May 22 at 3:45
  • \$\begingroup\$ So what are the timing parameters used for the external memory bus? Does it work if you add +1 to any of the current parameters? \$\endgroup\$
    – Justme
    Commented May 22 at 4:25
  • \$\begingroup\$ You’ve done simulations etc, but do the actual pcbs perform as per your simulations? You might be able to submit your design files to ST to validate. \$\endgroup\$
    – Kartman
    Commented May 22 at 9:15
  • \$\begingroup\$ Are the decoupling capacitors X7R type and are there enough? The impact on capacitance variation during temperature change is large compared to the impact on the IC. \$\endgroup\$
    – Jens
    Commented May 22 at 14:15
  • \$\begingroup\$ @Justme I will be requesting this parameter be updated. As I am aware, we are running at HCLK of 180 MHz. I would like to see what would happen if we increase timing parameters in bit error tests. \$\endgroup\$
    – Oscyzilla
    Commented May 22 at 14:48

0

Reset to default

Browse other questions tagged or ask your own question.