All Questions
28
questions
1
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89
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How are oscilloscopes able to fill DDR SDRAM memory without interruptions from memory refresh?
From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand ...
- 23
1
vote
1
answer
218
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What does transfer rate in RAM actually mean? How do you actually measure it?
From what I gather, transfer rate is how many bits you transfer via the bus at once with every clock. So the formula would be: frequency (in MHz) * 2 (because of DDR) * bus width (because I think it's ...
- 41
0
votes
1
answer
919
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DDRX Memory : What does DRAM prefetch mean? Also, why is the I/O bus clock half of the transfer rate?
While looking at the chart below, I had a question about DRAM prefetch & I/O Bus clock.
The characteristic of DDR is that it transfers 2 sets of data every cycle.
Therefore, for older versions of ...
- 1
5
votes
1
answer
1k
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Is my understanding of DRAM memory array topology in relation to "rows" and "columns" correct?
Assume a x16 DDR SDRAM module with 2b banks, which are made of 2r rows, which are further composed of 2c columns, where each column is 2w bits "tall". Assume that the interface is burst-...
- 203
2
votes
1
answer
635
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DDR3 Termination resistor value regarding
In a design, my senior put a 49.9ohm termination resistor to terminate the control, address, and control lines.Here I can't find the correct explation for this.
My question is,
1.How to choose the ...
- 21
1
vote
1
answer
261
views
DDR3 Termination Resistors and VTT Capacitors
I have a DDR3 implemented in our current design with 50 Ohm 0402 termination resistors and 0.1uF 0402 decoupling capacitors to VTT on the address, data and control lines. The design is working well ...
- 96
1
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0
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26
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DDR interfacing with rockers3399 processor
I am using rockers 3399 processor in one of my applications. if you see page no 9 'External Memory or Storage device' section you can see the below things
*Support 2 channels, each channel is 16 or ...
- 2,593
1
vote
1
answer
258
views
DDR3 logic levels - AC or DC?
In a DDR3 datasheet, I found different voltage levels (AC and DC.) I already know about DC logic levels but I don't know about AC logic levels.
What is the difference between the two?
Do the AC values ...
- 2,593
0
votes
1
answer
56
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DDR3 ECC 16gb 2rx4 PC3-14900r - Identification of the damaged chip by memory address
I got 4 16GB 2Rx4 PC3-14900R memory chips; Samsung M393B2G70DB0-CMA
Out of 4 memory sticks, 1 OK, 2 report ECC errors (correctable - 1bit), 1 dead.
I would like to replace the damaged chips. There are ...
1
vote
1
answer
757
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tRAS definition for DDR memory
In Figure 3 of https://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh , why tRAS is defined as the max timing between two REFRESH commands ? This ...
- 413
0
votes
2
answers
159
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ddr3 content after intialization
I am verifying a memory interface to MIG IP from Xilinx.
The MIG IP is connected to a ddr3 SDRAM from Micron. I have a ddr3 model from Micron that I included in my testbench.
I waited until the ...
3
votes
0
answers
136
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DDR3 SODIMM slow clock specification
I am considering to design memory controller handling 1GB of the RAM. I did already design controller for Micron's 32MB SDRAM in the past using Cyclone III device.
The new design is for retro ...
- 7,120
0
votes
1
answer
239
views
What is voltage level in DDR5 defined by JEDEC?
Voltage level in DDR4 is 1.2 volt, will it be same in DRR5 also? Also how much maximum voltage fluctuation will be allowed?
- 102
1
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1
answer
1k
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Theoretical calculation of DDR3L transfer speed
I am not sure if this questions belongs to this stack exchange site but I didn't find other better one. In case it doesn't, let me know and I will move it to some other place.
I am working with a ...
- 113
1
vote
1
answer
3k
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Why address mirroring in some SDRAMs?
I have seen references to that feature here and here (pg 20)
I can't quite get why it is useful. Since the memory controller selects the rank, wouldn't be the same if the address on the rank would ...
- 13