All Questions
44
questions
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89
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How are oscilloscopes able to fill DDR SDRAM memory without interruptions from memory refresh?
From the many teardown videos, it is clear that modern oscilloscopes mostly use DDR memory. But this memory needs to be refreshed periodically. Which should interrupt the data stream. I understand ...
- 23
0
votes
0
answers
27
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What is the DDR4/5 Colum-to-Column access latency for within bank access
Since DDR4, the banks are divided into bank-groups, where Column-to-Column delay (CCD) for accessing in different bank-groups is lower (tCCD_s) than than of accessing bank-to-bank within a bank-group (...
- 324
1
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0
answers
168
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Picking the best memory technology for our needs
This is my first post here, but bear with me. I have come here after searching the internet for a while (like most of us do)
We are in the process of figuring out which memory option would be the best ...
- 402
0
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1
answer
919
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DDRX Memory : What does DRAM prefetch mean? Also, why is the I/O bus clock half of the transfer rate?
While looking at the chart below, I had a question about DRAM prefetch & I/O Bus clock.
The characteristic of DDR is that it transfers 2 sets of data every cycle.
Therefore, for older versions of ...
- 1
0
votes
1
answer
179
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What are the options to interface Altera or Xilinx FPGA with a microprocessor or microcontroller?
I am trying to design a system which has some sensors connected to an FPGA and want to transfer the sensor data from the FPGA to a microprocessor like NXP IMX. I am new to FPGA and would like to know ...
- 75
3
votes
1
answer
228
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Why did GDDR5X implement QDR?
DDR makes complete sense to me: it matches up the transition rate between the data signals and clock, so that twice the data can be sent over a bus without increasing the overall design bandwidth. The ...
- 10.8k
1
vote
1
answer
399
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How much skew correction can typically be applied to DQS during DDR4 link training?
My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync.
Is there ...
- 10.8k
1
vote
0
answers
26
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DDR interfacing with rockers3399 processor
I am using rockers 3399 processor in one of my applications. if you see page no 9 'External Memory or Storage device' section you can see the below things
*Support 2 channels, each channel is 16 or ...
- 2,593
3
votes
2
answers
1k
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maximum memory supported by processor - why often stated less than 1TB?
I want to understand technical details of limitations of maximum memory size a system / processor can support. Below what I was able to find via web search to date Wiki:
Modern 64-bit processors such ...
- 247
2
votes
1
answer
161
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DDR4 Routing Consideration
I'm designing a new PC based on Intel Tiger Lake UP3.
In Intel Design Guide, I saw that there recommendation for DDR4 signals is to have two BO segments (BO1 and BO2).
each BO has different impedance ...
- 1,067
1
vote
1
answer
258
views
DDR3 logic levels - AC or DC?
In a DDR3 datasheet, I found different voltage levels (AC and DC.) I already know about DC logic levels but I don't know about AC logic levels.
What is the difference between the two?
Do the AC values ...
- 2,593
0
votes
1
answer
218
views
Is data width of an external DDR memory the same as the pins used to transfer data?
I'm trying to configure a Memory Interface Generator IP in Vivado. Somehow, the Block Automation doesn't work and I've to do it myself.
The board I'm using is the Arty A7 development board. It has a ...
- 237
2
votes
1
answer
2k
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The concept of DDR rank
I have an understanding of DDR rank which I think is incorrect. If someone could join the dots then there would be more clarity.
Here is what I know
A DDR rank is a 64bit interface consisting of x8 ...
- 379
1
vote
1
answer
94
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DDR5 Standard: Changelog
I would like to upgrade a software simulator from DDR4 to DDR5. I was looking for a document that describes in detail the changes of the DDR5 standard but I couldn't.
Is there any source that explains ...
- 121
1
vote
1
answer
757
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tRAS definition for DDR memory
In Figure 3 of https://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh , why tRAS is defined as the max timing between two REFRESH commands ? This ...
- 413