All Questions
38
questions
1
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166
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How to handle flash write/read operations on STM32L552 with ICACHE enabled without disabling it?
I am currently working with an STM32L552 microcontroller and encountering some peculiar behavior when writing and reading double words to and from the flash memory. After writing data to a specific ...
- 229
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0
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43
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Can we service another memory request from L1 cache when an L1 miss is being serviced from L2?
Consider the case where L1 cache miss occurred and is being serviced by L2 cache which could take many cycles (may go to main memory in case of L2 cache miss). In the meantime L1 cache is idle, in ...
- 137
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1
answer
1k
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How do computer memories interact with each other (registers, cache, RAM, ROM)?
After Googling around for some time, I have managed to get a good understanding what makes these components different, but I've yet to find any clear computer architecture-focused article/thread on ...
- 103
2
votes
1
answer
147
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Size of a memory cache
Assuming we have a virtual address issued by a model CPU that contains a total of 32 bits and 20 bits of this address are reserved for the tag + the cache comprises a total of 1024 cache lines.
Should ...
- 227
1
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0
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22
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Lines transferred from main memory to Cache
I'm studying Cache memories and I would like to know exactly how the lines are transferred from memory to cache.
Supposing I have a 32-bit machine with a 16kB directly mapped cache and 8 words per ...
- 1,431
1
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1
answer
5k
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In Directed-mapped cache, a problem in exercise!
5.2 Caches are important to providing a high-performance memory hierarchy
to processors. Below is a list of 32-bit memory address references, given as word
addresses.
3, 180, 43, 2, 191, 88, ...
- 111
1
vote
1
answer
491
views
How x86-64 Intel CPU understands how many bytes load into a register
I have the following byte code one the left and and its byte representation on the right:
...
- 130
6
votes
3
answers
4k
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What information exactly does an instruction cache store?
Processors use both data and instruction caches in order to reduce the number of slow accesses to main memory. However, while it is clear to me that the data cache's purpose is to store frequently ...
- 79
1
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0
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69
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How is CAM implemented?
I have a book statement:
A content addressable memory is a circuit that combines comparison and storage in a single device.
I want to know how this is implemented in real world? Sounds like an ...
- 221
-1
votes
1
answer
78
views
Cache memory on hit, no data stored
So, I have a question about the cache memory, i know that if the tag matches the data will be retrieved, but what happens if the current address has the same tag with others but in that place, in my ...
- 101
1
vote
1
answer
2k
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How much of a CPU die surface is taken by cache memory in modern microprocessors?
I am interested in how much of the surface of a modern or older CPU's are taken by cache memory ?
Are there any statistics regarding the size that cache memory takes in CPU dies of today ?
Are the ...
- 803
1
vote
2
answers
716
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Which cache type is better for bus watching?
I am studying for an exam about memory (mostly cache) and I ran across a multiple-choice question from a few years back:
...
- 163
0
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2
answers
1k
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Page table - I don't understand how this table has been made [closed]
CPU has generated this sequence of logic addresses (in decimal):
777, 2047, 1199, 1100, 546, 129, 3201
page size is 512 Byte, ...
- 113
1
vote
1
answer
739
views
Cache memory vs shadow RAM
I know that cache memory is much faster than typical RAMs. Apart from that, what exactly is the difference between Cache memory and shadow RAM? Both of them will have data that are to be accessed ...
- 741
2
votes
3
answers
4k
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Is cache memory unnecessary in microcontrollers?
Do we use cache memory in microcontrollers, if not, why not? If yes, what is its application in embedded systems or it is enough just to have RAM?
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