The bus clock rate is how many times per second data is transferred from one component to another. If we consider DRAM DDR4-3200, the clock frequency of the RAM bus today can be 1600 MHz at the same time the memory frequency is only 400 MHz, that is, the memory is able to store data in its cells with a frequency of 400 MHz. That is, in fact, the CPU is able to exchange data with RAM with a frequency of 1600 MHz, but the RAM frequency is much lower, how then the data manages to be saved in the memory cells?
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\$\begingroup\$ Please share which memory interface you are talking about, be specific. \$\endgroup\$– Voltage Spike ♦Commented Apr 23 at 15:32
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\$\begingroup\$ Are you perhaps talking about computer memory modules such as DDR4? \$\endgroup\$– JustmeCommented Apr 23 at 15:33
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2 Answers
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Here is a screenshot from the datasheet linked by Ale..chenski:
DQ (far right) are the output data pins, and there are 16 in total, so a 16 bit interface. However, the interface driving those 16 pins (read FIFO block) from the memory array is 128 bits wide, meaning it will read 8 times as many bytes as needed at a time. Thus it can run at at 1/8th the memory bus speed and still produce the needed data.
To plug in your numbers, if the array ran at 400 MHz, and the bus ran 8x this speed, that would be a 3200 MHz DRAM. Indeed, that datasheet is for a DDR4-3200 DRAM.
So to answer your question, the memory bus can be n times faster than the DRAM by putting n DRAM arrays in parallel and then muxing them onto the bus.
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\$\begingroup\$ I have one more question. We access different banks and read bytes from different banks, then how is the addressing organized? I mean, for example, that when writing 16 bytes to memory, the first byte will be written to the n-address of the first bank, and the second will also be written to the n-address of the second bank, etc.? \$\endgroup\$– SlaycapьCommented Apr 25 at 3:26
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\$\begingroup\$ @Slaycapь Consecutive bytes in one write go to the same bank, but you can change banks between writes. Ask a new question, someone more familiar with DDR4 specifically can explain it better than me. \$\endgroup\$ Commented Apr 25 at 4:46
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First, have you thought about the meaning of DDR? It is Dual Data Rate, which means two pieces of data per one clock. There are busses with Quad Data rate, same idea.
All your speculations about data transfer rates are wrong, it is much more complicated than that. Data transfer rate is not equivalent to clock of the interface. Please get any datasheet, say, for Micron DDR4 memory chips and look at timing diagrams presented there. You will see the gap between your questions/statements and reality.
answered Apr 23 at 16:27